Analysis of Hybrid SETMOS T-Gate using Quaternary Multiple Valued (MV) Logic
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In future nanometer technology, Single electron devices are promising device element to meet the demand for increasing in density, performance and power dissipation in ultra large scale integration. It appears that CMOS and SETs are rather complementary to each other; it is also true that combining SET and CMOS can provide a new functionality, which is un-mirrored in pure CMOS technology. SET with CMOS hybrid architecture is commonly referred to as SETMOS. It offer coulomb blockade oscillation and quasi periodic negative differential effect which gives an advantage to realize MV logic. Transmission (T)-gate act as universal gate which is implemented by using MV SETMOS. In this paper T-gate is proposed using literal gate of SETMOS device and its application such as single and two variables (multiple) function which act as basic blocks of sequential, logical circuits. Herein, the design functionality of quaternary multiple-valued logic is implemented by using voltage mode SETMOS. Analytical MIB model for SET is calibrated with BSIM 4.6.1 bulk MOSFET at 45 nm. The simulated waveform of circuits is carried out at room temperature in T-spice pro-environment. The proposed circuit with SETMOS device consumes merely 2050 nw of power along with 81 ps delay in comparison to its CMOS counterparts. Several intrinsic parameters (such as propagation delay, switching energy, area and voltage gain) play crucial role in determining the efficiency of the proposed quaternary MV logic T-gate is also investigated.
KeywordsMultiple-valued logic (MVL) Transmission (T) Gate Single electron transistor (SET) MIB Quaternary SETMOS Literal/universal literal gate
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