Frequency and Voltage Dependence of Interface States and Series Resistance in Ti/Au/p-Si Diodes with 100 μm and 200 μm Diameter Fabricated by Photolithography
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Ti/Au/p-Si diodes with the diameters of 100 and 200 μ m were fabricated by photolithographic technique. Capacitance–voltage (C–V) and conductance–voltage (G/w–V) characteristics of these diodes have been investigated by considering the series resistance (Rs) and interface states (Nss) effects. Experimental results show that the value of C and G/w in per area, with D1 (100 μ m) is lower than that of D2 (200 μ m) in depletion region but this behavior become reverse at accumulation region. Such behavior of C and G/w can be attributed to the special distribution of Nss at metal/semiconductor (M/S) interface, series resistance (Rs) of diode. The interface states density of the devices determined from high-low capacitance methods are presented for comparison. The voltage dependent profile of Rs was obtained for 100 kHz and 1 MHz. The observed anomalous peaks in C–V plots at 100 kHz were attributed to the effects of Rs, Nss and native interfacial layer. Experimental result show that the localizations of Nss at Ti/Au/p-Si interface, Rs and native interfacial layer have significant effects on the C–V and G/w–V characteristics of Ti/Au/p-Si diodes.
KeywordsTi/Au/p-Si SBDs High-low capacitance methods Interface states Series resistance Voltage dependent
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