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Mechanism for mitigating filler-induced reliability degradation in semiconductor devices assembled utilizing an LOC package technique

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Abstract

This work illustrates a mechanism for mitigating filler-induced reliability degradation in semiconductor devices assembled utilizing an LOC (lead-on-chip) package technique. Based on the mechanism, this article provides two fundamental solutions to solve the filler-driven problem in semiconductor products. First of all, in order to avoid filler-driven pattern damage during thermal-cycling, the maximum filler size in the plastic package body should have a diameter smaller than half of the inter-distance between the device pattern and it’s overlying lead-frame. Second, for effective prevention of filler-induced failure, the minimum distance between the polyimide coverage and each pad should be maintained to have a dimension that corresponds to the polyimide thickness. This article conclusively shows that the proper combination of two solutions can allow semiconductor products to have better reliability margins in use.

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Acknowledgments

This work was supported by Incheon National University fund for research year, 2017.

Author information

Correspondence to Seong-Min Lee.

Additional information

Recommended by Editor Chongdu Cho

Seong-Min Lee is a Professor of the Department of Materials Science and Engineering, Incheon National University, Incheon, Korea. He received his Ph.D. in Metallurgical Engineering from the University of Wisconsin-Madison, USA.

Yeon-Wook Kim is a Professor of the Department of Advanced Materials Engineering, Keimyung University, Deagu, Korea.

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Lee, S., Kim, Y. Mechanism for mitigating filler-induced reliability degradation in semiconductor devices assembled utilizing an LOC package technique. J Mech Sci Technol 34, 675–680 (2020). https://doi.org/10.1007/s12206-020-0113-8

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Keywords

  • Silicon wafer
  • Chip
  • Reliability
  • Semiconductor