Journal of Central South University

, Volume 26, Issue 1, pp 158–167 | Cite as

Electromagnetic emanation exploration in FPGA-based digital design

  • Van Toan Nguyen
  • Minh Tung Dam
  • Jeong-Gun LeeEmail author


As semiconductor technologies have been shrinking, the speed of circuits, integration density, and the number of I/O interfaces have been significantly increasing. As a consequence, electromagnetic emanation (EME) becomes a critical issue in digital system designs. Electronic devices must meet electromagnetic compatibility (EMC) requirements to ensure that they operate properly, and safely without interference. I/O buffers consume high currents when they operate. The bonding wires, and lead frames are long enough to play as efficient antennas to radiate electromagnetic interference (EMI). Therefore, I/O switching activities significantly contribute to the EMI. In this paper, we evaluate and analyze the impact of I/O switching activities on the EME. We will change the circuit configurations such as the supply voltage for I/O banks, their switching frequency, driving current, and slew rate. Additionally, a trade-off between the switching frequencies and the number of simultaneous switching outputs (SSOs) is also considered in terms of EME. Moreover, we evaluate the electromagnetic emissions that are associated with the different I/O switching patterns. The results show that the electromagnetic emissions associated I/O switching activities depend strongly on their operating parameters and configurations. All the circuit implementations and measurements are carried out on a Xilinx Spartan-3 FPGA.

Key words

electromagnetic interference electromagnetic emanation near field emissions field programmable gate array slew rate 

基于FPGA 数字设计的电磁辐射探索


随着半导体技术的不断萎缩,电路的速度、集成密度和I/O 接口的数量显著增加,因此,电磁 辐射(EME)成为数字系统设计中的一个关键问题。电子设备必须满足电磁兼容性(EMC)的要求,以确 保其正常运行,且不受干扰。I/O 缓冲器在工作时消耗大电流。连接线和引线框足够长,可以作为有 效的天线发射电磁干扰(EMI)。因此,I/O 交换活动对电磁干扰有显著影响。本文对I/O 交换活动对电 磁环境的影响进行了评价和分析。改变电路配置,如I/O 组的供电电压、他们的开关频率、驱动电流 和转换率。此外,还考虑了交换频率与同时交换输出(SSOs)数量之间的权衡问题。此外,还评估了与 不同I/O 开关模式相关的电磁辐射。结果表明,与I/O 开关活动相关的电磁辐射强烈依赖于他们的工 作参数和配置。所有电路实现和测量都是在Xilinx Spartan-3 FPGA 上进行的。


电磁干扰 电磁辐射 近场排放 现场可编程门阵列 转换速率 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    PILSOO L, JAE K L, KYOO Y L, INCHAE S, BOO G K. Analysis of EMI dependence on signal duty and supplied voltage [C]// IEEE Workshop on Signal Propagation on Interconnects. Strasbourg: IEEE, 2009: 1–4.Google Scholar
  2. [2]
    KIM N K, HWANG J S, KIM S Y. EMI prediction of slew-rate controlled I/O buffers by full-wave and circuit Co-simulation [J]. Journal of Semiconductor Technology and Science, 2014, 14(4): 471–477.CrossRefGoogle Scholar
  3. [3]
    CHAN R S, TAN N F, MOKHTAR M R. Simultaneous switching noise impact to signal eye diagram on high-speed I/O [C]// 4th Asia Symp on Quality Electronic Design. Penang: IEEE, 2012: 200–205.Google Scholar
  4. [4]
    HARUYA F, YO I, TOSHIO S. Measurement and analysis of SSN and Jitter of FPGA [C]// 2012 Int Symp on Electromagnetic Compatibility. Rome: IEEE, 2012: 1–6.Google Scholar
  5. [5]
    OIKAWA R, GOPE D, JANDHYALA V. Return-path extraction technique for SSO analysis of low-cost wire-bonding BGA packages [J]. IEEE Transaction on Components, Packaging and Manufacturing Technology, 2012, 2(4): 677–686.CrossRefGoogle Scholar
  6. [6]
    RAMDANI M, SICARD E, BOYER A, DHIAS B, WHALEN J J, HUBING T H, COENEN M, WADA O. The electromagnetic compatibility of integrated circuits-past, present, and future [J]. IEEE Transaction on Electromagnetic Compatibility, 2009, 51(1): 78–100.CrossRefGoogle Scholar
  7. [7]
    TAKUYA S, KUMPEI Y, HIDEHIRO T, KOJI N, MAKOTO N. An extended direct power injection method for in-place susceptibility characterization of VLSI circuits against electromagnetic interference [J]. IEEE Transaction on VLSI Systems, 2015, 23(10): 2347–2351.CrossRefGoogle Scholar
  8. [8]
    LEE J G. A low EMI circuit design with asynchronous multi-frequency clocking [J]. IEICE Transactions on Electron, 2014, E97-C(4): 1158–1161.CrossRefGoogle Scholar
  9. [9]
    KUMAR S, CHELLAPPA S, CLARK L T. Temporal pulse-clocked multi-bit flip-flop mitigating SET and SET [C]// 2015 IEEE Int Symp on Circuits and Systems (ISCAS). Lisbon: IEEE, 2015: 814–817.CrossRefGoogle Scholar
  10. [10]
    FUJITA H, TAKATANI H, TANAKA Y, SHOHEI K, MASAOMI S, TOSHIO S. Evaluation of PDN impedance and power supply noise for different on-chip decoupling structures [C]// 9th International Workshop on EMC of Integrated Circuit. Nara: IEEE, 2013: 142–146.Google Scholar
  11. [11]
    YASUHIRO O, MASANORI H, TOSHIKI K, TAKAO O. Supply noise suppression by triple-well structure [J]. IEEE Transaction on VLSI Systems, 2013, 21 (4): 781–785.Google Scholar
  12. [12]
    CARR J J. The technician’s EMI handbook: Clues and solutions [M]. Massachusetts: Newnes, 2000.Google Scholar
  13. [13]
    PARK H H, JANG H T, PARK H B, CHEOLSEUNG C H. An EMI evaluation method for integrated circuits in mobile devices [J]. IEEE Transaction on Electromagnetic Compatibility, 2013, 55 (4): 780–787.CrossRefGoogle Scholar
  14. [14]
    FANG Wen-xiao, SHI Chun-lei, CHEN Li-hui, EN Yun-fei, LIU Yuan, XIAO Qing-zhong. Near field characterization of the electromagnetic interference for a microcontroller [C]// 2014 Int Conference on Reliability, Maintainability and Safety (ICRMS). Guangzhou: IEEE, 2014: 32–35.CrossRefGoogle Scholar
  15. [15]
    LECA J P, FROIDEVAUX N, DUPRE P, GILLES J, HENRI B R. EMI measurement, modeling, and reduction of 32-Bit high-performance microcontrollers [J]. IEEE Transaction on Electromagnetic Compatibility, 2014, 56(5): 1035–1044.CrossRefGoogle Scholar
  16. [16]
    ALAELDINE A, LACRAMPE N, BOYAER A, PERDRIAU R, GAIGNET F, RAMDANI M, SICARD E, DRISSI M. Comparison among emission and susceptibility reduction techniques for electromagnetic interference in digital integrated circuits [J]. Elsevier Microelectronics Journal, 2008, 39: 1728–1735.CrossRefGoogle Scholar
  17. [17]
    GAO Xu, FANG Jun, ZHANG Yao-jiang, HAMED K, DAVID P. Far-field prediction using only magnetic near-field scanning for EMI test [J]. IEEE Transaction on Electromagnetic Compatibility, 2014, 56(6): 1335–1343.CrossRefGoogle Scholar
  18. [18]
    DC and switching characteristics (Spartan-3 FPGA family Datasheet) [R]. San Jose: Xilinx Inc., 2013.Google Scholar
  19. [19]
    SWAMINATHAN M, ENGIN A E. Power integrity modeling and design for semiconductors and systems [M]. Massachussetts: Prentice Hall, 2007.Google Scholar
  20. [20]
    DENG S, HUBING T, BEETNER D. Analysis of chip-level EMI using near-field magnetic scanning [C]// 2004 Int Symp on Electromagnetic Compatibility. Sendai: IEEE, 2004: 174–177.Google Scholar

Copyright information

© Central South University Press and Springer-Verlag GmbH Germany, part of Springer Nature 2019

Authors and Affiliations

  1. 1.E-SoC Laboratory/Smart Computing Laboratory, Department of Computer EngineeringHallym UniversityChuncheonKorea

Personalised recommendations