Field Stress Influenced Conduction Behavior of Narrow Diameter Gate-All-Around (GAA) Silicon Nanowire n-MOSFET
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Narrow diameter, n-channel gate-all-around (GAA) silicon nanowire metal–oxide–semiconductor-field-effect-transistor (GAA-SNWFET) shows partial surface conduction under constant field stress, which was validated from the low frequency noise measurements. The said conduction mode is different than the complete bulk mode of conduction as found in pre-stressed devices, and had been assessed from the normalized drain current power spectral density (PSD) versus frequency (f) and gate voltage overdrive [(VG − VT)] characteristics. In all instances followed by constant field stressing for different times, Lorentzian PSD was found, the low frequency component of which furthermore shows a direct deviation from its dependence on (VG − VT)−1, in contrary to the pre-stressed device. We explained the rationale of Lorentzian PSD from fresh trap creation inside the gate oxide of silicon nanowire under the influence of stress. Further, observed correlated variation between the normalized PSD versus time averaged drain current (<ID>) and, normalized transconductance versus <ID> supports trap influenced transport in the stressed device. Transient drain current with its statistical distribution of current levels for different VG − VT furthermore shows trap assisted partial surface conduction in stressed nanowire.
KeywordsSilicon nanowire field effect transistor low frequency noise drain current transient field stress
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The authors sincerely thank Dr. Navab Singh, Institute of Microelectronics (IME), Singapore, for the GAA-SNWFET fabrication support. The work has been funded through the Grant No. SR/FTP/ETA-0124/2013, SERB-DST, India.
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