An efficient and adaptable multimedia system for converting PAL to VGA in real-time video processing

  • Deepak Kumar JainEmail author
  • Sunil Jacob
  • Jafar Alzubi
  • Varun Menon
Special Issue Paper


Real-time video processing has found its range of applications from defense to consumer electronics for surveillance, video conferencing, etc. With the advent of Field Programmable Gate Arrays (FPGAs), flexible real-time video processing systems which can meet hard real-time constraints are easily realized with short development time. Most of the existing solutions have high utilization of system resources and are not quite flexible with many applications. Here we propose a hardware–software co-design for an FPGA-based real-time video processing system to convert video in standard Phase Alternating Line (PAL) 576i format to standard video of Video Graphics Array (VGA)/Super Video Graphics Array (SVGA) format with little utilization of resources. Switching between multiple video streams, character/text overlaying, and skin color detection are also incorporated with the system. The system is also adaptable for rugged applications. VHSIC Hardware Description Language (VHDL) codes for the architecture were synthesized using Altera Quartus II and targeted for Altera Stratix I FPGA. Results achieved confirm that the proposed system performs efficient conversion with very less resource utilization compared to the existing solutions. Since the proposed system is also flexible, many other applications can be incorporated in the future.


FPGA Hardware–software co-design PAL RTVPS VGA/SVGA VHDL 



  1. 1.
    Kehtarnavaz, N., Gamadia, M.: Real-time image and video processing: from research to reality. Synth Lectur Image Video Multimed Process 2(1), 1–108 (2006)CrossRefGoogle Scholar
  2. 2.
    Wenge, Z., Huiming, H.: FPGA-based video image processing system research. In: 2010 3rd International Conference on Computer Science and Information Technology, Chengdu, China, vol. 4, pp. 680–682. IEEE (2010)Google Scholar
  3. 3.
    Guo, X., Wei, X., Liu, Y.: An FPGA implementation of multi-channel video processing and 4 K real-time display system. In: 2017 10th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics (CISP-BMEI), Shanghai, China, pp. 1–6. IEEE (2017)Google Scholar
  4. 4.
    Seyid, K., Richaud, A., Capoccia, R., Leblebici, Y.: FPGA-based hardware implementation of real-time optical flow calculation. IEEE Trans. Circuits Syst. Video Technol. 28(1), 206–216 (2018)CrossRefGoogle Scholar
  5. 5.
    Draper, B.A., Beveridge, J.R., Bohm, A.W., Ross, C., Chawathe, M.: Accelerated image processing on FPGAs. IEEE Trans. Image Process. 12(12), 1543–1551 (2003)CrossRefGoogle Scholar
  6. 6.
    Kechiche, L., Touil, L., Ouni, B.: Real-time image and video processing: method and architecture. In: 2016 2nd International Conference on Advanced Technologies for Signal and Image Processing (ATSIP), Monastir, Tunisia, pp. 194–199. IEEE (2016)Google Scholar
  7. 7.
    MacLean, W.J.: An evaluation of the suitability of FPGAs for embedded vision systems. In: 2005 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR’05)-Workshops, San Diego, CA, USA, p. 131. IEEE (2005)Google Scholar
  8. 8.
    Poynton, C.A.: A Technical Introduction to Digital Video. Wiley, New York (1996)Google Scholar
  9. 9.
    Lawal, N., O’Nils, M.: Embedded FPGA memory requirements for real-time video processing applications. In: 2005 NORCHIP, pp. 206–209. IEEE (2005)Google Scholar
  10. 10.
    Zheng, J., Gan, J., Chen, L.: The design of PAL integrative camera based on FPGA. In: 2010 International Conference on Multimedia Technology, Ningbo, China, pp. 1–4 (2010)Google Scholar
  11. 11.
    Altera Corporation: Stratix device family data sheet. Stratix Device Handbook, vol. 1 (2004)Google Scholar
  12. 12.
    Rao, M.G., Kumar, P.R., Prasad, A.M.: Implementation of real time image processing system with FPGA and DSP. In: 2016 International Conference on Microelectronics, Computing and Communications (MicroCom), Durgapur, India, pp. 1–4. IEEE (2016)Google Scholar
  13. 13.
    Jinghong, D., Yaling, D., Kun, L.: Development of image processing system based on DSP and FPGA. In: 2007 8th International Conference on Electronic Measurement and Instruments, Xi’an, China, pp. 2–791. IEEE (2007)Google Scholar
  14. 14.
    Zhang, X., Li, X., Yang, W., Li, R.: FPGA-based color space conversion system design and implementation. In: 2016 IEEE 7th Annual Ubiquitous Computing, Electronics and Mobile Communication Conference (UEMCON), NewYork, USA, pp. 1–4. IEEE (2016)Google Scholar
  15. 15.
    Dong, H., Guo, H.: Design of VGA display controller based on FPGA and VHDL. In: 2011 International Conference on Electric Information and Control Engineering, Wuhan, China, pp. 4125–4128. IEEE (2011)Google Scholar
  16. 16.
    Wang, G., Guan, Y., Zhang, Y.: Designing of VGA character string display module based on FPGA. In: 2009 International Symposium on Intelligent Ubiquitous Computing and Education, Chengdu, China, pp. 499–502. IEEE (2009)Google Scholar
  17. 17.
    Bouganssa, I., Sbihi, M., Zaim, M.: Implementation on a FPGA of edge detection algorithm in medical image and tumors characterization. In: 2016 5th International Conference on Multimedia Computing and Systems (ICMCS), Marrakash, Morocco, pp. 59–64. IEEE (2016)Google Scholar
  18. 18.
    Khosravi, M.R., Yazdi, M.: A lossless data hiding scheme for medical images using a hybrid solution based on IBRW error histogram computation and quartered interpolation with greedy weights. Neural Comput. Appl. 30, 2017–2028 (2018)CrossRefGoogle Scholar
  19. 19.
    Khosravi, M.R., Sharif-Yazd, M., Moghimi, M.K., Keshavarz, A., Rostami, H., Mansouri, S.: MRF-based multispectral image fusion using an adaptive approach based on edge-guided interpolation. J. Geogr. Inf. Syst. 9(02), 114 (2017)Google Scholar
  20. 20.
    Rajesh, S., Paul, V., Menon, V.G., Khosravi, M.R.: A secure and efficient lightweight symmetric encryption scheme for transfer of text files between embedded IoT devices. Symmetry 11(2), 293 (2019)CrossRefGoogle Scholar
  21. 21.
    Khosravi, M.R., Rostami, H., Samadi, S.: Enhancing the binary watermark-based data hiding scheme using an interpolation-based approach for optical remote sensing images. Int. J. Agric. Environ. Inf. Syst. (IJAEIS) 9(2), 53–71 (2018)CrossRefGoogle Scholar
  22. 22.
    Alzubi, J., Jacob, S., Menon, V.G., Joseph, S., Vinoj, P.G.: A top-up design for pal to vga conversion in real time video processing system. In: 2018 International Symposium on Advanced Electrical and Communication Technologies (ISAECT), Rabat, Morocco, pp. 1–5. IEEE (2018)Google Scholar
  23. 23.
    Lan, X., Zhang, S., Yuen, P.C., Chellappa, R.: Learning common and feature-specific patterns: a novel multiple-sparse-representation-based tracker. IEEE Trans. Image Process. 27(4), 2022–2037 (2018)MathSciNetCrossRefzbMATHGoogle Scholar
  24. 24.
    Lan, X., Ye, M., Shao, R., Zhong, B., Yuen, P.C., Zhou, H.: Learning modality-consistency feature templates: a robust RGB-infrared tracking system. In: IEEE Transactions on Industrial ElectronicsGoogle Scholar
  25. 25.
    Lan, X., Ma, A.J., Yuen, P.C., Chellappa, R.: Joint sparse representation and robust feature-level fusion for multi-cue visual tracking. IEEE Trans. Image Process. 24(12), 5826–5841 (2015)MathSciNetCrossRefzbMATHGoogle Scholar
  26. 26.
    Lan, X., Ye, M., Zhang, S., Zhou, H., Yuen, P.C.: Modality-correlation-aware sparse representation for RGB-infrared object tracking. Pattern Recognit. Lett. (2018). Google Scholar
  27. 27.
    Jain, D.K., Zhang, Z., Huang, K.: Random walk-based feature learning for micro-expression recognition. Pattern Recogn. Lett. 115, 92–100 (2018)CrossRefGoogle Scholar
  28. 28.
    Jain, D.K., Zhang, Z., Huang, K.: Multi angle optimal pattern-based deep learning for automatic facial expression recognition. Pattern Recogn. Lett. (2017). Google Scholar
  29. 29.
    Ren, S., Jain, D.K., Guo, K., Xu, T., Chi, T.: Towards efficient medical lesion image super-resolution based on deep residual networks. Signal Process. Image Commun. (2019). Google Scholar
  30. 30.
    Menon, V.G., Prathap, J.: Vehicular fog computing: challenges applications and future directions. In: Fog Computing: Breakthroughs in Research and Practice, pp. 220–229. IGI Global, USA (2018)Google Scholar
  31. 31.
    Lawal, N.: Memory synthesis for fpga implementation of real-time video processing systems. Doctoral dissertation, Mid Sweden University (2009)Google Scholar
  32. 32.
    Chacko, B.T., Shelly, S.: Real-time video filtering and overlay character generation on FPGA. In: 2010 International Conference on Recent Trends in Information, Telecommunication and Computing, Kochi, India, pp. 184–189. IEEE (2010)Google Scholar
  33. 33.
    Fischer, V., Lukac, R., Martin, K.: Cost-effective video filtering solution for real-time vision systems. EURASIP J. Appl. Signal Process. 2005, 2026–2042 (2005)Google Scholar
  34. 34.
    Shi, D., Ye, X.: Design of VGA display system based on CPLD and SRAM. In: 2013 Third International Conference on Intelligent System Design and Engineering Applications, Hiongkong, pp. 579–582. IEEE (2013)Google Scholar
  35. 35.
    Kalomiros, J.A., Lygouras, J.: A host co-processor FPGA-based architecture for fast image processing. In: 2007 4th IEEE Workshop on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, Dortmund, Germany, pp. 373–378. IEEE (2007)Google Scholar
  36. 36.
    Ziting, W., Haili, G., Yan, S.: Design of VGA image controller based on SOPC technology. In: 2009 International Conference on New Trends in Information and Service Science, Beijing, China, pp. 825–827. IEEE (2009)Google Scholar
  37. 37.
    Aihua, W., Dong, L., Zhen, W.: The design Of VGA data communication based on FPGA. In: 2011 IEEE International Symposium on IT in Medicine and Education, Guanzhou, vol. 1, pp. 649–651. IEEE (2011)Google Scholar
  38. 38.
    Altera Corporation: Broadcast video infrastructure implementation using FPGAs. White paper, ver. 1.2Google Scholar
  39. 39.
    Joo, Y.M., McKeown, N.: Doubling memory bandwidth for network buffers. In: Proceedings. IEEE INFOCOM’98, the Conference on Computer Communications. Seventeenth Annual Joint Conference of the IEEE Computer and Communications Societies. Gateway to the 21st Century (Cat. No. 98), San Franscisco, CA, USA, vol. 2, pp. 808–815. IEEE (1998)Google Scholar
  40. 40.
    Altera Corporation: Video and image processing suite, User Guide (2009)Google Scholar

Copyright information

© Springer-Verlag GmbH Germany, part of Springer Nature 2019

Authors and Affiliations

  • Deepak Kumar Jain
    • 1
    Email author
  • Sunil Jacob
    • 2
  • Jafar Alzubi
    • 3
  • Varun Menon
    • 4
  1. 1.Key Laboratory of Intelligent Air-Ground Cooperative Control for Universities in Chongqing, College of AutomationChongqing University of Posts and TelecommunicationsChongqingChina
  2. 2.Center for RoboticsSCMS School of Engineering and TechnologyKeralaIndia
  3. 3.School of EngineeringAl-Balqa Applied UniversitySaltJordan
  4. 4.Department of Computer Science and EngineeringSCMS School of Engineering and TechnologyKeralaIndia

Personalised recommendations