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Journal of Real-Time Image Processing

, Volume 16, Issue 1, pp 71–80 | Cite as

VLSI implementation of anisotropic probabilistic neural network for real-time image scaling

  • Ching-Han Chen
  • Hsiang-Wen ChangEmail author
  • Chia-Ming Kuo
Special Issue Paper
  • 43 Downloads

Abstract

This study proposes an VLSI implementation of anisotropic probabilistic neural network (APNN) for real-time video processing applications. The APNN interpolation method achieves good sharpness enhancement at edge regions and reveals the noise reduction at smooth region. For real-time applications, the APNN interpolation is further implemented with efficient pipelined very-large-scale integration (VLSI) architecture. The VLSI architecture of APNN has a five-layer structure, which is comprised of Euclidian layer, Gaussian layer, weighting layer, summation layer, and division layer. The VLSI implementation outperforms software with the low-loss quality. The experimental results indicate that the performance of VLSI implementation is competent for image interpolation. The presented VLSI implementation of APNN interpolation method can reach \(1920\times 1080\) at 30 frames per second (FPS) with a reasonable hardware cost.

Keywords

Anisotropic Neural networks Interpolation Sharpness Smoothness 

References

  1. 1.
    Aibe, N., Yasunaga, M., Yoshihara, I., Kim, J.H.: A probabilistic neural network hardware system using a learning-parameter parallel architecture. In: Proceedings of the 2002 International Joint Conference on Neural Networks, 2002. IJCNN ’02, vol. 3, pp. 2270–2275 (2002)Google Scholar
  2. 2.
    Chen, C.H., Kuo, C.M., Yao, T.K., Hsieh, S.H.: Anisotropic probabilistic neural network for image interpolation. J. Math. Imaging Vis. 48(3), 488–498 (2014)MathSciNetCrossRefzbMATHGoogle Scholar
  3. 3.
    Dong, C., Loy, C.C., He, K., Tang, X.: Image super-resolution using deep convolutional networks. IEEE Trans. Pattern Anal. Mach. Intell. 38(2), 295–307 (2016).  https://doi.org/10.1109/TPAMI.2015.2439281 CrossRefGoogle Scholar
  4. 4.
    Hsieh, S.H., Chen, C.H.: Adaptive image interpolation using probabilistic neural network. Expert Syst. Appl. 36(3, Part 2), 6025–6029 (2009)CrossRefGoogle Scholar
  5. 5.
    Hsieh, S.H., Chen, C.H., Tseng, Y.W.: Adaptive edge enhancement based on anisotropic image interpolation. In: 2010 8th World Congress on Intelligent Control and Automation, pp. 3286–3290 (2010)Google Scholar
  6. 6.
    Ibrahim, M.N., Tack, C.K., Idroas, M., Bilmas, S.N., Yahya, Z.: Hardware implementation of math module based on cordic algorithm using FPGA. In: 2013 International Conference on Parallel and Distributed Systems, pp. 628–632 (2013)Google Scholar
  7. 7.
    Jamro, E., Wiatr, K., Wielgosz, M.: Fpga implementation of 64-bit exponential function for HPC. In: 2007 International Conference on Field Programmable Logic and Applications, pp. 718–721 (2007)Google Scholar
  8. 8.
    Keys, R.: Cubic convolution interpolation for digital image processing. IEEE Trans. Acoust. Speech Signal Process. 29(6), 1153–1160 (1981).  https://doi.org/10.1109/TASSP.1981.1163711 MathSciNetCrossRefzbMATHGoogle Scholar
  9. 9.
    Lee, S.J., Kang, M.C., Uhm, K.H., Ko, S.J.: An edge-guided image interpolation method using taylor series approximation. IEEE Trans. Consum. Electron. 62(2), 159–165 (2016)CrossRefGoogle Scholar
  10. 10.
    Lehmann, T.M., Gonner, C., Spitzer, K.: Survey: interpolation methods in medical image processing. IEEE Trans. Med. Imaging 18(11), 1049–1075 (1999).  https://doi.org/10.1109/42.816070 CrossRefGoogle Scholar
  11. 11.
    Minchin, G., Zaknich, A.: A design for FPGA implementation of the probabilistic neural network. In: 6th International Conference on Neural Information Processing, 1999. Proceedings. ICONIP ’99, vol. 2, pp. 556–559 (1999)Google Scholar
  12. 12.
    Munoz, D.M., Sanchez, D.F., Llanos, C.H., Ayala-Rincon, M.: FPGA based floating-point library for CORDIC algorithms. In: 2010 VI Southern Programmable Logic Conference (SPL), pp. 55–60 (2010)Google Scholar
  13. 13.
    Oberman, S.F., Flynn, M.J.: Division algorithms and implementations. IEEE Trans. Comput. 46(8), 833–854 (1997)MathSciNetCrossRefGoogle Scholar
  14. 14.
    Polat, O., Yıldırım, T.: FPGA implementation of a general regression neural network: an embedded pattern classification system. Digit. Signal Process. 20(3), 881–886 (2010)CrossRefGoogle Scholar
  15. 15.
    Qinglan, F., Yunfeng, Z., Xunxiang, Y., Fangxun, B., Xiaohong, S.: A new interpolation algorithm based on the frequency transform. In: 2016 IEEE 14th International Conference on Dependable, Autonomic and Secure Computing, 14th International Conference on Pervasive Intelligence and Computing, 2nd International Conference on Big Data Intelligence and Computing and Cyber Science and Technology Congress (DASC/PiCom/DataCom/CyberSciTech), pp. 217–222 (2016)Google Scholar
  16. 16.
    Specht, D.F.: Probabilistic neural networks for classification, mapping, or associative memory. In: IEEE 1988 International Conference on Neural Networks, vol. 1, pp. 525–532 (1988)Google Scholar
  17. 17.
    Sridhar, D., Krishna, I.M.: Brain tumor classification using discrete cosine transform and probabilistic neural network. In: 2013 International Conference on Signal Processing, Image Processing Pattern Recognition, pp. 92–96 (2013)Google Scholar
  18. 18.
    Sridhar, D., Krishna, I.M.: Face image classification using combined classifier. In: 2013 International Conference on Signal Processing, Image Processing Pattern Recognition, pp. 97–102 (2013)Google Scholar
  19. 19.
    Thevenaz, P., Blu, T., Unser, M.: Interpolation revisited [medical images application]. IEEE Trans. Med. Imaging 19(7), 739–758 (2000).  https://doi.org/10.1109/42.875199 CrossRefGoogle Scholar
  20. 20.
    Wang, D., Hao, Y., Zhu, X., Zhao, T., Wang, Y., Chen, Y., Chen, W., Zheng, X.: FPGA implementation of hardware processing modules as coprocessors in brain–machine interfaces. In: Conference proceedings:... Annual International Conference of the IEEE Engineering in Medicine and Biology Society, vol. 2011, p. 4613 (2011)Google Scholar
  21. 21.
    Xu, D., Zhang, X.: Study of MTF measurement technique based on special object image analyzing. In: 2012 IEEE International Conference on Mechatronics and Automation, pp. 2109–2113 (2012)Google Scholar
  22. 22.
    Zhou, F., Liu, J., Yu, Y., Tian, X., Liu, H., Hao, Y., Zhang, S., Chen, W., Dai, J., Zheng, X.: Field-programmable gate array implementation of a probabilistic neural network for motor cortical decoding in rats. J. Neurosci. Methods 185(2), 299–306 (2010)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag GmbH Germany, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Computer Science and Information EngineeringNational Central UniversityTaoyuan CountyTaiwan

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