Journal of Real-Time Image Processing

, Volume 14, Issue 3, pp 701–712 | Cite as

High-level synthesis for FPGAs: code optimization strategies for real-time image processing

  • Chao Li
  • Yanjing Bi
  • Yannick Benezeth
  • Dominique Ginhac
  • Fan Yang
Special Issue Paper

Abstract

High-level synthesis (HLS) is a potential solution to increase the productivity of FPGA-based real-time image processing development. It allows designers to reap the benefits of hardware implementation directly from the algorithm behaviors specified using C-like languages with high abstraction level. In order to close the performance gap between the manual and HLS-based FPGA designs, various code optimization forms are made available in today’s HLS tools. This paper proposes a HLS source code and directive manipulation strategy for real-time image processing by taking into account the applying order of different optimization forms. Experiment results demonstrate that our approach can improve more effectively the test implementations comparing to the other optimization strategies.

Keywords

Code optimization High-level synthesis FPGA Real-time image processing 

Notes

Acknowledgements

The authors would like to thank the China Scholarship Council, the CAS Pioneer Hundred Talents Program and the Conseil Régional de Bourgogne Franche-Comté for their funding of our studies.

References

  1. 1.
    Wang, H., Zhang, N., Crput, J.C., Moreau, J., Ruichek, Y.: Parallel structured mesh generation with disparity maps by gpu implementation. IEEE Trans. Visual Comput. Graph. 21(9), 1045–1057 (2015)CrossRefGoogle Scholar
  2. 2.
    Wang, H.: Cellular matrix for parallel k-means and local search to Euclidean grid matching. Theses, Université de Technologie de Belfort-Montbéliard. https://tel.archives-ouvertes.fr/tel-01265951 (December 2015)
  3. 3.
    Li, C., Brost, V., Benezeth, Y., Marzani, F., Yang, F.: Design and evaluation of a parallel and optimized light-tissue interaction-based method for fast skin lesion assessment. J Real Time Image Process. 1–14 (2015). doi: 10.1007/s11554-015-0494-6
  4. 4.
    Li, C., Balla-Arabé, S., Yang, F.: Embedded multi-spectral image processing for real-time medical application. J. Syst. Archit. 64, 26–36. (2015). http://www.sciencedirect.com/science/article/pii/S1383762115001526
  5. 5.
    Li, C., Balla-Arabé, S., Ginhac, D., Yang, F.: Embedded implementation of vhr satellite image segmentation. Sensors 16(6), 771 (2016). http://www.mdpi.com/1424-8220/16/6/771
  6. 6.
    Wakabayashi, K.: Use of high-level synthesis to generate hardware from software. IEICE ESS Fundam. Rev. 6(1), 37–50 (2012)CrossRefGoogle Scholar
  7. 7.
    Cong, J., Liu, B., Neuendorffer, S., Noguera, J., Vissers, K., Zhang, Z.: High-level synthesis for FPGAS: from prototyping to deployment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(4), 473–491 (2011)CrossRefGoogle Scholar
  8. 8.
    Koichi, F., Kazushi, K., Shin-ya, A., Masao, Y., Togawa, N.: A floorplan-driven high-level synthesis algorithm for multiplexer reduction targeting fpga designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. E98.A(7), 1392–1405 (2015)CrossRefGoogle Scholar
  9. 9.
    Cong, J., Liu, B., Prabhakar, R., Zhang, P.: A study on the impact of compiler optimizations on high-level synthesis. In: Kasahara, H., Kimura, K. (eds.) Languages and Compilers for Parallel Computing, Series Lecture Notes in Computer Science, vol. 7760, pp. 143–157. Springer, Berlin (2013). doi: 10.1007/978-3-642-37658-0_10
  10. 10.
    Keisuke, I., Mineo, K.: Dual-edge-triggered flip-flop-based high-level synthesis with programmable duty cycle. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. E96.A(12), 2689–2697 (2013)CrossRefGoogle Scholar
  11. 11.
    Vivado Design Suite User Guide, Ug902 (2012.2) ed., XILINX, (July 2012)Google Scholar
  12. 12.
    Wang, G.: Catapult C Synthesis Work Flow Tutorial, Version 1.3 ed., ECE Department, Rice University (October 2010)Google Scholar
  13. 13.
    Wakabayashi, K.: C-based behavioral synthesis and verification analysis on industrial design examples. In: Proceedings of the 2004 Asia and South Pacific Design Automation Conference, Series ASP-DAC ’04, pp. 344–348. IEEE Press, Piscataway (2004). http://dl.acm.org/citation.cfm?id=1015090.1015177
  14. 14.
    Villarreal, J., Park, A., Najjar, W., Halstead, R.: Designing modular hardware accelerators in c with ROCCC 2.0. In: 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 127–134 (May 2010)Google Scholar
  15. 15.
    Liang, Y., Rupnow, K., Li, Y., Min, D., Do, M.N., Chen, D.: High-level synthesis: productivity, performance, and software constraints. J. Electr. Comput. Eng., 2012, 14 (2012), article ID 649057. doi: 10.1155/2012/649057
  16. 16.
    Cong, J., Huang, M., Zou, Y.: Accelerating fluid registration algorithm on multi-FPGA platforms. In: 2011 International Conference on Field Programmable Logic and Applications (FPL), pp. 50–57 (September 2011)Google Scholar
  17. 17.
    Rupnow, K., Liang, Y., Li, Y., Min, D., Do, M., Chen, D.: High level synthesis of stereo matching: productivity, performance, and software constraints. In: 2011 International Conference on Field-Programmable Technology (FPT). IEEE (2011)Google Scholar
  18. 18.
    Rodrigues, R., Cardoso, J., Diniz, P.: A data-driven approach for pipelining sequences of data-dependent loops. In: 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2007. FCCM 2007, pp. 219–228 (April 2007)Google Scholar
  19. 19.
    Ziegler, H., Hall, M. W., Diniz, P.: Compiler-generated communication for pipelined FPGA applications. In: Design Automation Conference, 2003. Proceedings, pp. 610–615 (June 2003)Google Scholar
  20. 20.
    Cong, J., Fan, Y., Han, G., Jiang, W., Zhang, Z.: Behavior and communication co-optimization for systems with sequential communication media. In Design Automation Conference, 2006 43rd ACM/IEEE, pp. 675–678 (2006)Google Scholar
  21. 21.
    Li, P., Pouchet, L.-N., Cong, J.: Throughput optimization for high-level synthesis using resource constraints. In: IMPACT 2014. Fourth International Workshop on Polyhedral Compilation Techniques. In conjunction with HiPEAC 2014, Vienna, Austria (January 20, 2014)Google Scholar
  22. 22.
    Huang, Q., Lian, R., Canis, A., Choi, J., Xi, R., Calagar, N., Brown, S., Anderson, J.: The effect of compiler optimizations on high-level synthesis-generated hardware. ACM Trans. Reconfigurable Technol. Syst. 8(3), 14:1–14:26 (2015). doi: 10.1145/2629547 CrossRefGoogle Scholar
  23. 23.
    Gajski, D.D., Dutt, N.D., Wu, A.C.H., Lin, S.Y.L.: High-Level Synthesis: Introduction to Chip and System Design. Springer, New York (1992)CrossRefGoogle Scholar
  24. 24.
    Mehrara, M., Jablin, T., Upton, D., August, D., Hazelwood, K., Mahlke, S.: Multicore compilation strategies and challenges. Sig. Process. Mag. IEEE 26(6), 55–63 (2009)CrossRefGoogle Scholar
  25. 25.
    Ahn, J.H., Erez, M., Dally, W.J.: Tradeoff between data-, instruction-, and thread-level parallelism in stream processors. In: Proceedings of the 21st Annual International Conference on Supercomputing, Series ICS ’07, pp. 126–137. ACM, New York (2007). doi: 10.1145/1274971.1274991
  26. 26.
    Xilinx: Introduction to FPGA design with vivado high-level synthesis. Xilinx, Technical Report UG998 (v1.0) (July 2013)Google Scholar
  27. 27.
    Zuo, W., Liang, Y., Li, P., Rupnow, K., Chen, D., Cong, J.: Improving high level synthesis optimization opportunity through polyhedral transformations. In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Series FPGA ’13, pp. 9–18. ACM, New York (2013). doi: 10.1145/2435264.2435271
  28. 28.
    Pouchet, L.-N.: PoCC. The Polyhedral Compiler Collection., version 1.2 ed., on line, Computer Science Department, University of California Los Angeles, 4731L Boelter Hall, Los Angeles, CA 90095. http://www.cs.ucla.edu/pouchet/software/pocc/
  29. 29.
    Steven Derrien, A.M., Kumar, A.: S2s4hls-sp1 progress report. INRIA—University of Rennes 1, INRIA—ENS Cachan and INRIA—LIP, Technical Report (2008)Google Scholar
  30. 30.
    Morvan, A., Derrien, S., Quinton, P.: Efficient nested loop pipelining in high level synthesis using polyhedral bubble insertion. In: 2011 International Conference on Field-Programmable Technology (FPT), pp. 1–10 (December 2011)Google Scholar
  31. 31.
    Alle, M., Morvan, A., Derrien, S.: Runtime dependency analysis for loop pipelining in high-level synthesis. In: Design Automation Conference (DAC), 2013 50th ACM/EDAC/IEEE, pp. 1–10 (May 2013)Google Scholar
  32. 32.
    Vivado Design Suite Tutorial, Ug871(v2012.2) ed., XILINX (February 2012)Google Scholar
  33. 33.
    Lee, J.-H., Hsu, Y.-C., Lin, Y.-L.: A new integer linear programming formulation for the scheduling problem in data path synthesis. In: 1989 IEEE International Conference on Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers, pp. 20–23 (November 1989)Google Scholar

Copyright information

© Springer-Verlag GmbH Germany 2017

Authors and Affiliations

  1. 1.Stat Key Laboratory of Acoustics, Institute of AcousticsChinese Academy of SciencesBeijingChina
  2. 2.LE2I FRE2005 CNRS, Arts et MétiersUniv. Bourgogne Franche-ComtéDijonFrance
  3. 3.Laboratory of CPTCUniv. Bourgogne Franche-ComtéDijonFrance

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