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Journal of Real-Time Image Processing

, Volume 16, Issue 2, pp 391–411 | Cite as

Efficient reference frame compression scheme for video coding systems: algorithm and VLSI design

  • Dieison SilveiraEmail author
  • Guilherme Povala
  • Lívia Amaral
  • Bruno Zatt
  • Luciano Agostini
  • Marcelo Porto
Original Research Paper

Abstract

One of the most concerning issues in current video coding systems relies on the bottleneck caused by the intense external memory access required by motion estimation. As memory access affects directly the energy consumption, this problem becomes more evident when battery-powered devices are considered. In this sense, this article presents the Double Differential Reference Frame Compressor (DDRFC), which is a low-complexity and lossless solution to compress the reference frames before storing them in the external memory. The DDRFC performs intra-block double differential coding over 64 × 64-sample blocks to prepare the data for a static Huffman coding. The DDRFC guarantees block-level random access by avoiding data dependencies between neighboring blocks. It reaches an average compression ratio of 69 % for luminance samples for 1080 p video sequences, outperforming any lossless reference frame compressor available in the current literature. Hardware architectures for both the DDRFC encoder and decoder were designed and synthesized targeting FPGA and ASIC 180 and 65-nm standard cells libraries. The synthesis results show that with 65 nm, the DDRFC architectures are able to process 2160 p video at 30 FPS or 1080 p at 120 FPS with a power dissipation of 5.01 mW. The DDRFC codec reaches more than 68 % of energy savings when considering memory communication for HD and UHD video processing.

Keywords

Video coding HEVC Lossless reference frame compression Memory bandwidth reduction Hardware design Differential coding Huffman coding 

Notes

Acknowledgments

This work was partially financed by the National Council for Scientific and Technological Development (CNPq), Coordination of Improvement of Superior Education Staff (CAPES) and Research Support Foundation of Rio Grande do Sul (FAPERGS).

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Copyright information

© Springer-Verlag Berlin Heidelberg 2015

Authors and Affiliations

  • Dieison Silveira
    • 1
    • 2
    Email author
  • Guilherme Povala
    • 1
  • Lívia Amaral
    • 1
  • Bruno Zatt
    • 1
  • Luciano Agostini
    • 1
  • Marcelo Porto
    • 1
  1. 1.Group of Architectures and Integrated Circuits – GACIFederal University of Pelotas – UFPelPelotasBrazil
  2. 2.Institute of InformaticsFederal University of Rio Grande do Sul – UFRGSPorto AlegreBrazil

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