Model-Based Design of Flexible and Efficient LDPC Decoders on FPGA Devices

  • Yann Delomier
  • Bertrand Le GalEmail author
  • Jérémie Crenne
  • Christophe Jego


Advances in digital communication advocate for the use of hardware LDPC decoders in applications requiring reliable and fast information transfer. Hand-coded RTL architectures provide the highest performances but slower the path to IP design. By the use of HLS-based methodology, a number of approaches exists to facilitate development and to rapidly incorporate hardware accelerators into end-user applications. In this paper we present a generic SystemC behavioral model to generate efficient hardware LDPC decoders using Xilinx Vivado HLS. We evaluate the performance of provided architectures and assess efficiency over competing approaches. Hardware complexity reduction up to 10× are shown whereas the throughput speedups are between 1.5× and 16×. The provided architectures have performance in the same order of magnitude of handcrafted RTL architectures.


LDPC codes Model-based design HLS FPGA 



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© Springer Science+Business Media, LLC, part of Springer Nature 2020

Authors and Affiliations

  1. 1.IMS laboratory-UMR 5218, Bordeaux-INPUniv. of BordeauxTalenceFrance

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