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Low Power AES Using 8-Bit and 32-Bit Datapath Optimization for Small Internet-of-Things (IoT)

  • Ho Keun Kim
  • Myung Hoon SunwooEmail author
Article
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Abstract

This paper proposes a low-power advanced encryption standard (AES) that can be utilized in smaller applications such as small-scale internet- of-things (IoT) devices. The proposed AES uses 8-bit and 32-bit datapaths to satisfy low power consumption and small area requirements. We use the 32-bit datapath in MixColumns only; the 8-bit datapath was used in other blocks such as SubBytes, Byte Permutation, AddRoundKey, and KeyExpansion. In addition, we propose optimized SubBytes and MixColumns to achieve low power consumption within a small area. To optimize SubBytes, we simplify the algorithm block-by-block to decrease the area. For the MixColumns, we present a 32-bit datapath that uses the proposed 0 × 02 and 0 × 03 multiplier. The AES that we have presented in this study, is implemented through Verilog-HDL and synthesized using the Samsung 65 nm standard cell library. The proposed AES shows 5400 2-input NAND gate equivalences and a power consumption of 10.01 μW (@ 0.9 V) at 10 MHz.

Keywords

Advanced encryption standards (AES) Low power SubBytes MixColumns Small internet-of-things (IoT) 

Notes

Acknowledgments

This research was supported by the Ministry of Science and ICT (MSIT), Korea, under the Information Technology Research Center (ITRC) support program (IITP-2019-2016-0-00309) supervised by the Institute for Information & communications Technology Planning & Evaluation (IITP) and the National Research Foundation of Korea by the Korea government (NRF-2017R1A2A2A05001046).

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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.School of Electronics and Computer EngineeringAjou UniversitySuwonSouth Korea

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