Low Power AES Using 8-Bit and 32-Bit Datapath Optimization for Small Internet-of-Things (IoT)
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This paper proposes a low-power advanced encryption standard (AES) that can be utilized in smaller applications such as small-scale internet- of-things (IoT) devices. The proposed AES uses 8-bit and 32-bit datapaths to satisfy low power consumption and small area requirements. We use the 32-bit datapath in MixColumns only; the 8-bit datapath was used in other blocks such as SubBytes, Byte Permutation, AddRoundKey, and KeyExpansion. In addition, we propose optimized SubBytes and MixColumns to achieve low power consumption within a small area. To optimize SubBytes, we simplify the algorithm block-by-block to decrease the area. For the MixColumns, we present a 32-bit datapath that uses the proposed 0 × 02 and 0 × 03 multiplier. The AES that we have presented in this study, is implemented through Verilog-HDL and synthesized using the Samsung 65 nm standard cell library. The proposed AES shows 5400 2-input NAND gate equivalences and a power consumption of 10.01 μW (@ 0.9 V) at 10 MHz.
KeywordsAdvanced encryption standards (AES) Low power SubBytes MixColumns Small internet-of-things (IoT)
This research was supported by the Ministry of Science and ICT (MSIT), Korea, under the Information Technology Research Center (ITRC) support program (IITP-2019-2016-0-00309) supervised by the Institute for Information & communications Technology Planning & Evaluation (IITP) and the National Research Foundation of Korea by the Korea government (NRF-2017R1A2A2A05001046).
- 8.Agwa, S., Yahya, E., & Ismail, Y. (2017). Power efficient AES core for IoT constrained devices implemented in 130nm CMOS. In Proc. 2017 IEEE ISCAS, Baltimore, pp. 1–4.Google Scholar
- 9.National Institute of Standard Technology (NIST) (2001). Federal Information Processing Standards (FIPS) publication 197. Advanced Encryption Standard.Google Scholar
- 12.El-meligy, N., Anin, M., Yahya, E., & Ismail, Y. (2017). 130nm low power asynchronous AES Core. In Proc. 2017 IEEE ISCAS, Baltimore, pp. 1–4.Google Scholar
- 14.Hocquet, C., Kamel, D., Regazzoi, F., Legat, J., Flandre, D., Bol, D., & Standaert, F. (2011). Harvesting the potential of nano-CMOS for lightweight cryptography an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags. JCEN, 1(1), 79–86.Google Scholar
- 15.Shastry, P., Agnihotri, A., Kachhwaha, D., Singh, J., & Sutaone, M. (2011). A combinational logic implementation of S-box of AES. In Proc. 2011 IEEE 54th International MWSCAS, Seoul, pp. 1–4.Google Scholar
- 16.Zhao, W., Ha, Y., & Alioto, M. (2015). AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption. In Proc. 2015 IEEE ISCAS, Lisbon, pp. 2349–2352.Google Scholar
- 17.Mathew, S., Satpathy, S., Suresh, V., Anders, M., Kaul, H., Agarwal, A., Hsu, S., Chen, G., & Krishnamurthy, R. (2015). 340 mV-1.1 V, 289 Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(24)2 polynomials in 22 nm tri-gate CMOS. IEEE Journal of Solid-State Circuits, 50(4), 1048–1058.CrossRefGoogle Scholar