Power-effective ROM-less DDFS Design Approach with High SFDR Performance
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A ROM-less direct digital frequency synthesizer (DDFS) design approach based on interpolation schemes is proposed in this work. Besides achieving higher SFDR (spurious free dynamic range) and faster clock rate, detailed power estimation approach based on switching activity analysis of each logic sub-blocks is presented to explore the optimal solution. The parabolic equations with proper selection of coefficients and pipeline structure are utilized to enhance SFDR. A ROM-less DDFS using the proposed design approach is demonstrated by the physical implementation on Altera FPGA platform. The average SFDR is measured to be 68.4242 dBc with 1.1659 dBc deviation over 33 times of experiments. The measured SFDR is proved to outperform many previous DDFS works even if they were implemented on silicon.
KeywordsROM-less DDFS Spurious free dynamic range (SFDR) Parabolic polynomial interpolation Pipeline structure Power estimation
This investigation is partially supported by Ministry of Science and Technology, Taiwan, under grant MOST 107-2218-E-110-004- and 107-2221-E-006-232-. The authors would also like to express their deepest gratefulness to Chip Implementation Center of National Applied Research Laboratories, Taiwan, for their thoughtful chip fabrication service and EDA tool support.
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