Advertisement

Application-Specific Tailoring of Multi-Core SoCs for Real-Time Systems with Diverse Predictability Demands

  • Steffen Vaas
  • Peter Ulbrich
  • Marc Reichenbach
  • Dietmar Fey
Article

Abstract

Embedded multi-core processors improve performance significantly and are desirable in many application-fields. This development, in particular, includes safety-critical real-time systems, which typically require a deterministic temporal behavior. However, even tasks without dependencies running on different cores can interfere due to, sometimes hidden, shared hardware resources, such as memory or communication buses. Consequently, only a pessimistic assumption of the worst-case execution time (WCET) that incorporates interference can be given. The desired performance gain therefore evaporates in the poor temporal analyzability. Safety-critical real-time systems are typically composed of multiple tasks with varying criticality levels and requirements on predictability and performance, respectively. In this paper, we present an approach that generates an application-specific, deterministic multi-core architecture for such mix-critical systems, thus eliminating the aforementioned hardware-induced interferences in the first place. Safety-critical tasks with stringent temporal requirements are mapped to dedicated Deterministic Execution Units (DEUs) while the remaining soft real-time tasks co-reside on a general purpose multi-core processor that offers performance over determinism. Just as well, predictable interconnections between DEUs are generated to satisfy dependencies and precedence constraints. Consequently, timing analysis for hard real-time tasks is significantly simplified, since interferences caused by shared resources and scheduling are finally eliminated. To show the benefits of our approach, an application-specific architecture for a flight controller was generated and compared to an ARM Cortex-A9 dual-core as a reference. Overall, we were able to significantly improve temporal properties of safety-critical tasks while preserving the overall performance for soft real-time tasks.

Keywords

Safety-Critical Reconfigurable Reliable Deterministic Distributed NoC SoC 

Notes

Acknowledgments

This work is supported by the German Research Foundation (DFG) under grants no. SCHR 603/9-2, the Transregional Collaborative Research Centre “Invasive Computing” (SFB/TR89, Project C1), the Bavarian Ministry of State for Economics under grant no. 0704/883 25 (EU EFRE funds) and by the Bavarian Research Foundation (BFS) as part of their research project “FORMUS3 IC”.

References

  1. 1.
  2. 2.
  3. 3.
    Castrillon, J., Sheng, W., Jessenberger, R., Thiele, L., Schorr, L., Juurlink, B., Alvarez-Mesa, M., Pohl, A., Reyes, V., Leupers, R. (2015). Multi/many-core programming: where are we standing?. In 2015 design, automation test in Europe conference exhibition (DATE) (pp. 1708–1717).  https://doi.org/10.7873/DATE.2015.1129.
  4. 4.
    Ferdinand, C., Heckmann, R., Wolff, H.J., Renz, C., Parshin, O., Wilhelm, R. (2008). Towards model-driven development of hard real-time systems. In Model-driven development of reliable automotive services (pp. 145–160). Springer.Google Scholar
  5. 5.
    Fernandez, G., Abella, J., Quiñones, E., Rochange, C., Vardanega, T., Cazorla, F.J. (2014). Contention in multicore hardware shared resources: understanding of the state of the art. In 14th international workshop on worst-case execution time analysis, OpenAccess Series in Informatics (OASIcs) (pp. 31–42): Schloss Dagstuhl–Leibniz-Zentrum für Informatik.  https://doi.org/10.4230/OASIcs.WCET.2014.31. http://drops.dagstuhl.de/opus/volltexte/2014/4602
  6. 6.
    Fernández, M., Gioiosa, R., Quiñones, E., Fossati, L., Zulianello, M., Cazorla, F.J. (2012). Assessing the suitability of the NGMP multi-core processor in the space domain. In Proceedings of the tenth ACM international conference on embedded software, EMSOFT ’12 (pp. 175–184). New York: ACM.  https://doi.org/10.1145/2380356.2380389. http://doi.acm.org/10.1145/2380356.2380389
  7. 7.
  8. 8.
    Kerrison, S., May, D., Eder, K. (2016). A Benes Based NoC switching architecture for mixed criticality embedded systems. In 2016 IEEE 10th international symposium on embedded multicore/many-core systems-on-chip (MCSOC) (pp. 125–132).  https://doi.org/10.1109/MCSoC.2016.50
  9. 9.
    Lee, E., Reineke, J., Zimmer, M. (2017). Abstract PRET machines. In 2017 IEEE real-time systems symposium (RTSS) (pp. 1–11) .  https://doi.org/10.1109/RTSS.2017.00041.
  10. 10.
    Liu, I., Reineke, J., Lee, E.A. (2010). A PRET architecture supporting concurrent programs with composable timing properties. In 2010 conference record of the forty fourth Asilomar conference on signals, systems and computers (pp. 2111–2115)  https://doi.org/10.1109/ACSSC.2010.5757922.
  11. 11.
    Mollison, M.S., Erickson, J.P., Anderson, J.H., Baruah, S.K., Scoredos, J.A. (2010). Mixed-criticality real-time scheduling for multicore systems. In 2010 10th IEEE international conference on computer and information technology (pp. 1864–1871)  https://doi.org/10.1109/CIT.2010.320
  12. 12.
    Montag, P., & Altmeyer, S. (2011). Precise WCET calculation in highly variant real-time systems (pp. 1–6). Design, Automation Test in Europe.  https://doi.org/10.1109/DATE.2011.5763149
  13. 13.
    OSEK/VDX Group. (2005). Operating system specification 2.2.3. Tech. rep., OSEK/VDX Group. http://portal.osek-vdx.org/files/pdf/specs/os223.pdf, visited 2014-09-29.
  14. 14.
    Pfundt, B., Reichenbach, M., Hartmann, C., Häublein, K., Fey, D. (2016). Teaching heterogeneous computer architectures using smart camera systems. In 2016 11th European workshop on microelectronics education (EWME).  https://doi.org/10.1109/EWME.2016.7496484.
  15. 15.
    Position Paper CAST-32A. https://www.faa.gov/aircraft/air_cert/design_approvals/air_software/cast/cast_papers/media/cast-32A.pdf. Certification Authorities Software Team (CAST).
  16. 16.
    Schoeberl, M., Pezzarossa, L., Sparsø, J. (2018). A multicore processor for time-critical applications. IEEE Design Test, 35(2), 38–47.  https://doi.org/10.1109/MDAT.2018.2791809.CrossRefGoogle Scholar
  17. 17.
    Schreiner, S., Grüttner, K., Rosinger, S., Rettberg, A. (2014). Autonomous flight control meets custom payload processing: a mixed-critical avionics architecture approach for civilian UAVs. In IEEE 17th international symposium on object/component/service-oriented real-time distributed computing (pp. 348–357).  https://doi.org/10.1109/ISORC.2014.28
  18. 18.
    Tobuschat, S., Axer, P., Ernst, R., Diemer, J. (2013). IDAMC: a NoC for mixed criticality systems. In 2013 IEEE 19th international conference on embedded and real-time computing systems and applications (pp. 149–156).  https://doi.org/10.1109/RTCSA.2013.6732214
  19. 19.
    Ungerer, T., Cazorla, F., Sainrat, P., Bernat, G., Petrov, Z., Rochange, C., Quinones, E., Gerdes, M., Paolieri, M., Wolf, J., Casse, H., Uhrig, S., Guliashvili, I., Houston, M., Kluge, F., Metzlaff, S., Mische, J. (2010). Merasa: multicore execution of hard real-time applications supporting analyzability. IEEE Micro, 30(5), 66–75.  https://doi.org/10.1109/MM.2010.78.CrossRefGoogle Scholar
  20. 20.
    Vaas, S., Reichenbach, M., Margull, U., Fey, D. (2016). The R2-D2 toolchain—automated porting of safety-critical applications to FPGAs. In 2016 international conference on reconfigurable computing and FPGAs (ReConFig).  https://doi.org/10.1109/ReConFig.2016.7857192.
  21. 21.
    Vaas, S., Ulbrich, P., Reichenbach, M., Fey, D. (2017). The best of both: high-performance anc deterministic real-time executive by application-specific multi-core socs. In 2017 conference on design and architectures for signal and image processing (DASIP).  https://doi.org/10.1109/DASIP.2017.8122107.
  22. 22.
  23. 23.
    Zimmer, M., Broman, D., Shaver, C., Lee, E.A. (2014). FlexPRET: a processor platform for mixed-criticality systems. In 2014 IEEE 19th real-time and embedded technology and applications symposium (RTAS) (pp. 101–110) .  https://doi.org/10.1109/RTAS.2014.6925994

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  • Steffen Vaas
    • 1
  • Peter Ulbrich
    • 2
  • Marc Reichenbach
    • 1
  • Dietmar Fey
    • 1
  1. 1.Chair of Computer Science 3 - Computer ArchitectureFriedrich-Alexander-University (FAU) Erlangen-NürnbergErlangenGermany
  2. 2.Chair of Computer Science 4 - Distributed Systems and Operating SystemsFriedrich-Alexander-University (FAU) Erlangen-NürnbergErlangenGermany

Personalised recommendations