An FPGA design and implementation of EPZS motion estimation algorithm for 3D H.264/MVC standard

  • N. A. BahranEmail author
  • W. El-Shafai
  • A. Zekry
  • S. El-Rabaie
  • M. M. El-Halawany
  • F. E. Abd El-Samie


In the Three-Dimensional H.264 Multi-view Video Coding (3D H.264/MVC), the original 3D Video (3DV) sequence is a combination of variable video frames captured for the same object by different cameras. Therefore, in order to transmit 3DV content over limited-resources networks, a highly-efficient compression mechanism must be applied, while achieving a better reception quality. Moreover, in real-time applications such as 3DV conference and streaming, it is mandatory that the process of 3DV compression/decompression is speedy. Because it is known that most of the design complexity of the utilized 3D H.264/MVC codec come from the encoder part not from the decoder part, where the Motion Estimation (ME) process presents the highest computational complexity. In this work, an efficient implementation of the Enhanced Predictive Zonal Search (EPZS) ME algorithm is introduced for the 3D H.264/MVC standard. The EPZS algorithm is one of the most common and best ME algorithms. The overall inter-frame and inter-view prediction mechanisms including Motion Compensation (MC) and ME have been implemented. For validation and comparative analysis purposes, the outcomes of the suggested 3DV design for the EPZS ME algorithm are contrasted to more state-of-the-art ME algorithms. The suggested architecture of the EPZS ME algorithm is implemented in VHDL, synthesized utilizing Xilinx Virtex-6 FPGA and Xilinx ISE Design Suite 13.3, simulated employing ModelSim SE 6.5, and validated utilizing MATLAB SIMULINK. Experimental results prove that the suggested architecture achieves a low hardware complexity implementation and high-speed of 3D H.264/MVC compression process. This can be exploited for the utilization of the proposed work for real-time 3DV applications.


3D video Motion compensation and estimation 3D H.264/MVC standard EPZS FPGA 



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© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Department of Electronics and Communications Engineering, Faculty of EngineeringAin Shams UniversityCairoEgypt
  2. 2.Department of Electronics and Electrical Communications Engineering, Faculty of Electronic EngineeringMenoufia UniversityMenoufEgypt

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