Journal of Medical Systems

, 43:31 | Cite as

An Optimized S-Box Circuit for High Speed AES Design with Enhanced PPRM Architecture to Secure Mammographic Images

  • T. Manojkumar
  • P. Karthigaikumar
  • Varatharajan RamachandranEmail author
Image & Signal Processing
Part of the following topical collections:
  1. Advancements in Internet of Medical Things for Healthcare System


In AES, the total time taken by the architecture while implementing in low power and high-speed circuit is the most important thing that to be considered. Also in AES, implementing S-Boxes consumes the major part of the total time consumed by the entire architecture. In this research paper, we propose a very low-power and high efficient S-Box circuit architecture: a multi-stage modified version of PPRM architecture over composite fields. In this modified S box design, only AND and Hazard transparent XOR gates are used. Because of this architecture dynamic hazards which form the main aspect of power consumption in S box gets eliminated. A low propagation delay of 4.58 ns and occupies 120 slices in the xilinx FPGA device xc6vlx75t-3ff784, while the low propagation delay and slice area is 5.552 ns and 120 respectively for the conventional PPRM architecture. This new proposed architecture is used to protect the mammographic images from being unauthorized access.


Advanced encryption standard Positive polarity reed muller S-Box Hazard Field programmable gate array Application specific integrated circuits BDD SOP Data encryption standard Pipeline architecture Mammographic images 



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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  • T. Manojkumar
    • 1
  • P. Karthigaikumar
    • 1
  • Varatharajan Ramachandran
    • 2
    Email author
  1. 1.Department of Electronics and Communication EngineeringKarpagam College of EngineeringCoimbatoreIndia
  2. 2.Department of Electronics and Communication EngineeringSri Ramanujar Engineering CollegeKancheepuramIndia

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