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A novel method for source/drain ion implantation for 20 nm FinFETs and beyond

  • Changliang Qin
  • Huaxiang YinEmail author
  • Guilei WangEmail author
  • Yanbo Zhang
  • Jinbiao Liu
  • Qinzhu Zhang
  • Huilong Zhu
  • Chao Zhao
  • Henry H. Radamson
Article
  • 9 Downloads

Abstract

This paper presents a method to improve source/drain extension (SDE) ion implantation (I/I) process for sub-20 nm node FinFETs with no extra step in transistor process. Traditionally, SDE I/I process needs a large implant tilt angle and a high dose to obtain a heavy and conformal doping. However, this process leads to implantation shadow effects and Si-fin amorphization. These drawbacks can be removed in our new approach when SDE I/I is modified and moved after S/D epitaxy process (SDE I/I-last). Because of the facet planes of the SiGe layer, the ions are allowed to be implanted with small tilt. This is helpful to avoid shadow effects of implantation and to keep the low defect density in the S/D. As a result, the external resistance (REXTRNL) is not high and the strain relaxation is minor in S/D epitaxy layer. Finally, p-type FinFETs with 25 nm gate length with SDE I/I-last are fabricated. These new FinFETs demonstrate ~ 50% on-state current (ION) improvement compared to those transistors fabricated by traditional method.

Notes

Acknowledgements

This work was financially supported by the National Key Research and Development Program of China (2016YFA0301701), and the Youth Innovation Promotion Association of CAS under Grant No 2016112, which are acknowledged.

References

  1. 1.
    T. Matsukawa, K. Endo, Y. Ishikawa, H. Yamauchi, S. O’uchi, Y. Liu, J. Tsukada, K. Ishii, K. Sakamoto, E. Suzuki, M. Masahara, Fluctuation analysis of parasitic resistance in FinFETs with scaled fin thickness. IEEE Electron Device Lett. 30(4), 407–409 (2009).  https://doi.org/10.1109/led.2009.2014180 CrossRefGoogle Scholar
  2. 2.
    G.L. Wang, M. Moeen, A. Abedin, M. Kolahdouz, J. Luo, C.L. Qin, H.L. Zhu, J. Yan, H.Z. Yin, J.F. Li, C. Zhao, H.H. Radamson, Optimization of SiGe selective epitaxy for source/drain engineering in 22 nm node complementary metal-oxide semiconductor (CMOS). J. Appl. Phys. 114(12), 123511 (2013)CrossRefGoogle Scholar
  3. 3.
    H.H. Radamson, L. Thylen, Monolithic Nanoscale Photonics-Electronics Integration in Silicon and Other Group 1 V Elements (Elsevier, Amsterdam, 2014)Google Scholar
  4. 4.
    G.L. Wang, A. Abedin, M. Moeen, M. Kolahdouz, J. Luo, Y. Guo, T. Chen, H. Yin, H. Zhu, J. Li, C. Hao, H.H. Radamson, Integration of highly-strained SiGe materials in 14 nm and beyond nodes FinFET technology. Solid-State Electron. 103, 222–228 (2015)CrossRefGoogle Scholar
  5. 5.
    Henry H. Radamson, E. Simoen, J. Luo, CMOS past, present and future [M] (Woodhead Publishing, Sawston, 2018)Google Scholar
  6. 6.
    J. Mody, A.K. Kambham, G. Zschatzsch, P. Schatzer, T. Chiarella, N. Collaert, L. Witters, M. Jurczak, N. Horiguchi, M. Gilbert, P. Eyben, S Kolling, A. Schulze, T-Y. Hoffmann, W. Vandervorst, Dopant and carrier profiling in FinFET-based devices with sub-nanometer resolution, in Proc. IEEE VLSIT, June 2010, pp. 407–409.  https://doi.org/10.1109/vlsit.2010.5556225
  7. 7.
    G. Zschatzsch, Y. Sasaki, S. Hayashi, M. Togo, T. Chiarella, A. K. Kambham, J. Mody, B. Douhard, N. Horiguchi, B. Mizuno, M. Ogura, W. Vandervorst, High performance n-MOS finFET by damage-free, conformal extension doping, in Proc. IEEE IEDM., Dec. 2011, pp. 841–844Google Scholar
  8. 8.
    L. Pelaz, L. Marques, M. Aboy, P. Lopez, I. Santos, R. Duffy, Atomistic process modeling based on Kinetic Monte Carlo and Molecular Dynamics for optimization of advanced devices, in Proc. IEEE IEDM., Dec. 2009, pp. 513–516.  https://doi.org/10.1109/iedm.2009.5424309
  9. 9.
    Pelaz, R. Duffy, M. Aboy, L. Marques, P. Lopez, I. Santos, B. J. Pawlak, M. J. H. van Dal, B. Duriez, T. Merelle, G. Doornbos, N. Collaert, L. Witters, R. Rooyackers, W. Vandervorst, M. Jurczak, M. Kaiser, R. G. R. Weemaes, J. G. M. van Berkum, P. Breimer, R. J. P. Lander, Atomistic modeling of impurity ion implantation in ultra-thin-body Si devices, in Proc. IEEE IEDM, Dec 2008, pp. 1–4.  https://doi.org/10.1109/iedm.2008.4796744
  10. 10.
    R. Duffy, G. Curatola, B.J. Pawlak, G. Doornbos, K. van der Tak, P. Breimer, J.G.M. van Berkum, F. Roozeboom, Doping fin field-effect transistor sidewalls: impurity dose retention in silicon due to high angle incident ion implants and the impact on device performance. J. Vac. Sci. Technol., B 26(1), 402–407 (2008).  https://doi.org/10.1116/1.2816925 CrossRefGoogle Scholar
  11. 11.
    H. Kawasaki, M. Khater, M. Guillorn, N. Fuller, J. Chang, S. Kanakasabapathy, L. Chang, R. Muralidhar, K. Babich, Q. Yang, J. Ott, D. Klaus, E. Kratschmer, E. Sikorski, R. Miller, R. Viswanathan, Y. Zhang, J. Silverman, Q. Ouyang, A. Yagishita, M. Takayanagi, W. Haensch, K. Ishimaru, Demonstration of highly scaled FinFET SRAM Cells with High-K/metal gate and investigation of characteristic Variability for the 32 nm node and beyond, in Proc. IEEE IEDM, Dec 2008, pp. 237–240.  https://doi.org/10.1109/iedm.2008.4796661
  12. 12.
    Y. Sasaki, L. Godet, T. Chiarella, D. P. Brunco, T. Rockwell, J. W. Lee, B. Colombeau, M. Togo, S. A. Chew, G. Zschaetszch, K. B. Noh, A. De Keersgieter, G. Boccardi, M. S. Kim, G. Hellings, P. Martin, W. Vandervorst, A. Thean, N. Horiguchi, Improved sidewall doping of extensions by AsH3 ion assisted deposition and doping (IADD) with small implant angle for scaled NMOS Si bulk FinFETs, in Proc. IEEE IEDM, Dec 2013, pp. 542–545.  https://doi.org/10.1109/iedm.2013.6724671
  13. 13.
    H. Onoda, Y. Nakashima, T. Nagayama, S. Sakai, High dose dopant implantation to heated si substrate without amorphous layer formation, in Proc. IEEE IWJT, June 2013, pp. 66–69.  https://doi.org/10.1109/iwjt.2013.6644507
  14. 14.
    R.H. Dennard, F.H. Gaensslen, V.L. Rideout, E. Bassous, A.R. LeBlanc, Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE J. Solid State Circ. 9(5), 256–268 (1974).  https://doi.org/10.1109/jssc.1974.1050511 CrossRefGoogle Scholar
  15. 15.
    L. Pelaz, L. Marques, I. Santos, P. Lopez, M. Aboy, Modeling of advanced Ion implantation technologies in semiconductors, in Proc. IEEE IWJT, June 2011, pp. 34–39.  https://doi.org/10.1109/iwjt.2011.5969995
  16. 16.
    J.-W. Han, J. Lee, D. Park, Y.-K. Choi, Body thickness dependence of impact ionization in a multiple-gate FinFET. IEEE Electron Device Lett. 28(7), 625–627 (2007).  https://doi.org/10.1109/led.2007.898284 CrossRefGoogle Scholar
  17. 17.
    G.K. Reeves, H.B. Harrison, Obtaining the specific contact resistance from transmission line model measurements. IEEE Electron Device Lett. 3(5), 111–113 (1982).  https://doi.org/10.1109/edl.1982.25502 CrossRefGoogle Scholar
  18. 18.
    C. Chang, T. Lee, C. Wann, L. Lai, H. Chen, C. Yeh, C. Chang, C. Ho, J. Sheu, T. Kwok, F. Yuan, S. Yu, C. Hu, J. Shen, Y. Liu, C. Chen, S. Chen, L. Chen, L. Chen, Y. Chiu, C. Fu, M. Huang, Y. Huang, S. Hung, J. Liaw, H. Lin, H. Lin, L. Lin, S. Lin, Y. Mii, E. Ou-Yang, M. Shieh, C. Su, Shih-Peng Tai, H. Tao, M. Tsai, K. Tseng, K. Wang, S. Wang, Jeff J. Xu, F. Yang, S. Yang, C. Yeh, A 25-nm gate-length FinFET transistor module for 32 nm Node, in Proc. IEEE IEDM, Dec 2009, pp. 293–296.  https://doi.org/10.1109/iedm.2009.5424367
  19. 19.
    T.-K. Kang, Evidence for silicon bandgap narrowing in uniaxially strained MOSFETs subjected to tensile and compressive stress. IEEE Electron Device Lett. 33(6), 770–772 (2012).  https://doi.org/10.1109/led.2012.2191759 CrossRefGoogle Scholar
  20. 20.
    M. Furuhashi, K. Taniguchi, Additional stress-induced band gap narrowing in a silicon die. J. Appl. Phys. 103(2), 026103-1-026103-3 (2008).  https://doi.org/10.1063/1.2833435 CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  • Changliang Qin
    • 1
    • 2
  • Huaxiang Yin
    • 1
    • 2
    Email author
  • Guilei Wang
    • 1
    • 2
    Email author
  • Yanbo Zhang
    • 1
  • Jinbiao Liu
    • 1
  • Qinzhu Zhang
    • 1
  • Huilong Zhu
    • 1
    • 2
  • Chao Zhao
    • 1
    • 2
  • Henry H. Radamson
    • 1
    • 2
    • 3
  1. 1.Key laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of SciencesBeijingPeople’s Republic of China
  2. 2.University of Chinese Academy of Sciences, Chinese Academy of SciencesBeijingPeople’s Republic of China
  3. 3.Department of Electronics DesignMid Sweden UniversitySundsvallSweden

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