Assess low-k/ultralow-k materials integrity by shear test on bumps of a chip
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The low-k/ultralow-k (LK/ULK) dielectric materials are introduced in the back-end of line (BEOL) to reduce the R-C delay in a chip with 40 nm technology node and beyond. The chips are generally packaged using a flip-chip technology, in which copper pillars are electrical connections and mechanical supports. Owing to the thermal mismatch between materials, copper pillars are sheared and higher stresses arise near the roots of the copper pillars, which causes cracks in LK/ULK materials that are porous and fragile in mechanics. In this study a rapid mechanical shear test of a copper pillar was proposed to mimic the corresponding shear force due to a temperature drop by finite element analysis (FEA) and bump shear experiments. FEA results for shear tests are in compliance with that of experiments and the high stress regions are conformed to the failure locations in the BEOL. Using the verified finite element models, a linear relationship between the shear force, the shear height and the temperature differential was built by keeping a bump in a same shear impact, which is valid for the temperature differential within 120 °C. In the suitable temperature range a mechanical shear test can quickly assess the failure possibility of LK/ULK materials caused by a temperature differential for evaluating their reliability in BEOL of an advanced chip.
The financial supports of National Nature Science Foundation of China (No. 61774044) and National Science and Technology Major Project of China (No. 2017ZX02315005) are greatly acknowledged.
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