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Equivalence Checking and Compaction of n-input Majority Terms Using Implicants of Majority

  • Rajeswari DevadossEmail author
  • Kolin Paul
  • M. Balakrishnan
Article
  • 19 Downloads

Abstract

Recent advances in nanotechnology have led to the emergence of energy efficient circuit technologies like spintronics and domain wall magnets that use Majority gates as their primary logic elements. For logic synthesis methods targeted to such technologies to be effective and efficient, they need to be able to use, manipulate, and exploit large Majority terms in their synthesis flow. One of the problems that turn up in such an endeavor is the determination of equivalence of two n-input Majority terms. As Majority gates implement more complex Boolean functions than traditional AND/OR gates, this is a non-trivial problem—one that demands to be solved before proceeding to harder problems dealing with networks of Majority gates. We provide an algorithm based on prime implicants as a solution to this problem. In addition, we provide an algorithm that compacts an n-input Majority term to an equivalent n-input Majority term that has the fewest number of inputs. In this quest, we extend the concept of implicants to two cases — 1-implicants and prime 1-implicants that imply that a function evaluates to ‘1’, and 0-implicants and prime 0-implicants that imply that it evaluates to ‘0’. We exploit the properties of Majority to create an efficient algorithm to generate the sums of all prime 1-implicants and all prime 0-implicants of an n-input Majority term. As Majority and Threshold functions have been shown to be logically equivalent, our algorithms are applicable to Threshold functions as well. Being based on implicants of Majority, our algorithms improve on the known naive algorithms for equivalence checking and compaction for threshold logic terms.

Keywords

Majority Threshold Prime implicants Implicants Canonical form Equivalence checking Compaction Minimization 

Notes

References

  1. 1.
    Akeela R, Wagh MD (2011) A five-input majority gate in quantum-dot cellular automata. In: NSTI Nanotech, vol 2, pp 978–981Google Scholar
  2. 2.
    Devadoss R, Paul K, Balakrishnan M (2015) Majsynth : an n-input majority algebra based logic synthesis tool for quantum-dot cellular automata. In: Proc. 24th international workshop on logic synthesis, 2015. IWLS’15Google Scholar
  3. 3.
    Devadoss R, Paul K, Balakrishnan M (2019) Majority logic: prime implicants and n-input majority term equivalence. In: Proc. 32nd International conference on VLSI design and 2019 18th international conference on embedded systems (VLSID). IEEE, pp 464–469Google Scholar
  4. 4.
    Gowda T, Vrudhula S, Konjevod G (2007) Combinational equivalence checking for threshold logic circuits. In: Proceedings of the 17th ACM great lakes symposium on VLSI. ACM, pp 102–107Google Scholar
  5. 5.
    Hulgaard H, Williams PF, Andersen HR (1999) Equivalence checking of combinational circuits using boolean expression diagrams. IEEE Trans Comput-Aided Design Integrated Circ Sys 18(7):903–917CrossRefGoogle Scholar
  6. 6.
    Kang W, Zhang Y, Wang Z, Klein JO, Chappert C, Ravelosona D, Wang G, Zhang Y, Zhao W (2015) Spintronics: emerging ultra-low-power circuits and systems beyond mos technology. J Emerg Technol Comput Syst 12(2):16:1–16:42CrossRefGoogle Scholar
  7. 7.
    Muroga S (1971) Threshold logic and its applications, Wiley-Interscience, New YorkGoogle Scholar
  8. 8.
    Sharad M, Augustine C, Panagopoulos G, Roy K (2012) Proposal for neuromorphic hardware using spin devices. CoRR, Cornell University. arXiv:1206.3227
  9. 9.
    Zhang R, Walus K, Wang W, Jullien GA (2004) A method of majority logic reduction for quantum cellular automata. IEEE Transactions on Nanotechnology 3(4):443–450CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Department of Computer Science and EngineeringIIT DelhiNew DelhiIndia

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