16- Layer PCB Channel Design with Minimum Crosstalk and Optimization of VIA and TDR Analysis
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A transparent interconnects on a 16 layer PCB stack-up with a 100 Ω differential impedance with interconnects is proposed in this paper. To minimize the differential crosstalk, a differential spacing is maintained between interconnects. The transmitter and receiver are demonstrated as Input Buffer Information Specification (IBIS) models. An IBIS model describes the V-I characteristics information about the particular buffer. To provide better channel performance, the interconnect Via structures are optimized in this paper. To observe the channel performance in the frequency domain, S-parameter analysis is performed. To view BER plots, eye diagram and bathtub curve analysis is implemented. To observe the impedance with respect to the propagation delay of the channel, Time Domain Reflectometer (TDR) analysis is performed. Debugging and impedance discontinuity correction are performed using TDR analysis. ADS 9 (Advanced Design System) simulation software is used in this paper.
KeywordsCrosstalk Insertion loss PCB stack-up Surface roughness S-parameters TDR analysis Trace Via
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