16- Layer PCB Channel Design with Minimum Crosstalk and Optimization of VIA and TDR Analysis

  • A. KavithaEmail author
  • Ch. Sekhararao Kaitepalli
  • J. N. Swaminathan
  • Shaik Ahemedali


A transparent interconnects on a 16 layer PCB stack-up with a 100 Ω differential impedance with interconnects is proposed in this paper. To minimize the differential crosstalk, a differential spacing is maintained between interconnects. The transmitter and receiver are demonstrated as Input Buffer Information Specification (IBIS) models. An IBIS model describes the V-I characteristics information about the particular buffer. To provide better channel performance, the interconnect Via structures are optimized in this paper. To observe the channel performance in the frequency domain, S-parameter analysis is performed. To view BER plots, eye diagram and bathtub curve analysis is implemented. To observe the impedance with respect to the propagation delay of the channel, Time Domain Reflectometer (TDR) analysis is performed. Debugging and impedance discontinuity correction are performed using TDR analysis. ADS 9 (Advanced Design System) simulation software is used in this paper.


Crosstalk Insertion loss PCB stack-up Surface roughness S-parameters TDR analysis Trace Via 



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Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringVel Tech Multi Tech Dr. Rangarajan Dr. Sakunthala Engineering CollegeChennaiIndia
  2. 2.Department of Electronics and Communication EngineeringAnna UniversityChennaiIndia
  3. 3.Department of Electronics and Communication EngineeringGodavari Institute of Engineering Technology (Autonomous)RajamundryIndia
  4. 4.Department of Electronics and Communication EngineeringSasi Institute of Technology & EngineeringTadepalligudemIndia

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