Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits

  • Shuo CaiEmail author
  • Weizheng Wang
  • Fei Yu
  • Binyong He


As the feature size of CMOS transistors scales down, Single Event Transient (SET) has been an important consideration in designing modern radiation tolerant circuits because it may cause some failures in the circuit outputs. Many researches have been done in analyzing the impact of SET on nanometer CMOS circuits. However, it is difficult to consider numerous factors such as three fault masking effects, consecutive cycles, signal correlations and so on. In this paper, we have presented a new approach for analyzing the propagation probabilities of SET in logic circuits. All three fault masking effects have been considered uniformly and SET Propagation Probabilities Matrices (SPPMs) have been used to represent the SET Propagation Probabilities (SPPs) in current clock cycle. Based on the matrix union operations which we have defined, the SPPs in consecutive cycles can be calculated accurately and efficiently. Experimental results on ISCAS’89 benchmark circuits show that our approach is practicable.


Single event transient (SET) Propagation probability matrix Masking effect Matrix union operation Logic circuits 



This research was supported in part by the National Natural Science Foundation of China (NSFC) under grant No.61702052, 61504013, in part by the Scientific Research Fund of Hunan Provincial Education Department under grant No.18A137, 17B011 and in part by the Open Research Fund of Hunan Provincial Key Laboratory of Intelligent Processing of Big Data on Transportation.


  1. 1.
    Alexandrescu D, Costenaro E, Evans A (2013) State-aware single event analysis for sequential logic. In: Proc. of IEEE 19th International On-Line Testing Symposium, pp. 151–156Google Scholar
  2. 2.
    Anglada M, Canal R, Aragón J L, González A (2016) MASkIt: Soft error rate estimation for combinational circuits. In: Proc of IEEE International Conference on Computer Design, pp. 614–621Google Scholar
  3. 3.
    Anglada M, Canal R, Aragón JL, González A (2018) Fast and accurate SER estimation for large combinational blocks in early stages of the design. IEEE Trans on Sustainable Computing.
  4. 4.
    Asadi H, Tahoori MB (2010) Soft error modeling and remediation techniques in asic designs. Microelectron J 41(8):506–522CrossRefGoogle Scholar
  5. 5.
    Asadi H, Tahoori MB, Fazeli M, Miremadi SG (2012) Efficient algorithms to accurately compute derating factors of digital circuits. Microelectron Reliab 52:1215–1226CrossRefGoogle Scholar
  6. 6.
    Cai S, Yu F, Wang WZ, Liu TQ, Liu P, Wang W (2017) Reliability evaluation of logic circuits based on transient faults propagation metrics. IEICE Electron Express 14(7):1–7CrossRefGoogle Scholar
  7. 7.
    Calomarde A, Amat E, Moll F, Vigara J, Rubio A (2014) SET and noise fault tolerant circuit design techniques: application to 7 nm FinFET. Microelectron Reliab 54(4):738–745CrossRefGoogle Scholar
  8. 8.
    Dhillon YS, Dril AU, Chatterjee A (2006) Analysis and optimization of nanometer CMOS circuits for soft-error tolerance. IEEE Trans on Very Large Scale Integr(VLSI) Syst 14(5):514–524CrossRefGoogle Scholar
  9. 9.
    Ferlet-Cavrois V, Massengill L, Gouker P (2013) Single event transients in digital CMOS—A review. IEEE Trans on Nucl Sci 60(3):1767–1790CrossRefGoogle Scholar
  10. 10.
    George N, Lach J (2011) Characterization of logic masking and error propagation in combinational circuits and effects on system vulnerability. In: Proc. of IEEE/IFIP Dependable Systems & Networks, pp. 323–334Google Scholar
  11. 11.
    Gill B, Seifert N, Zia V (2009) Comparison of alpha-particle and neutron-induced combinational and sequential logic error rates at the 32nm technology node. In: Proc. of IEEE 47th Annual International Reliability Physics Symposium, pp. 199–205Google Scholar
  12. 12.
    Grosso M, Guzman-Miranda H, Aguirre M (2013) Exploiting fault model correlations to accelerate SEU sensitivity assessment. IEEE Trans on Industrial Information 9(1):142–148CrossRefGoogle Scholar
  13. 13.
    Huang KH, Hu Y, Li XW (2014) Reliability-oriented placement and routing algorithm for SRAM-based FPGAs. IEEE Trans on Very Large Scale Integr (VLSI) Syst 22(2):256–269CrossRefGoogle Scholar
  14. 14.
    Ibrahim W, Shousha M, Chinneck JW (2015) Accurate and efficient estimation of logic circuits reliability bounds. IEEE Trans on Computers 64(5):1217–1229MathSciNetCrossRefzbMATHGoogle Scholar
  15. 15.
    Koren I, Krishna CM (2007) Fault-Tolerant Systems. Morgan Kaufman, San FranciscozbMATHGoogle Scholar
  16. 16.
    Krishnaswamy S, Viamontes GF, Markov IL, Hayes JP (2008) Probabilistic transfer matrices in symbolic reliability analysis of logic circuits. ACM Trans Design Autom Electron Syst 13(1):8CrossRefGoogle Scholar
  17. 17.
    Liang JH, Han J, Lombardi F (2013) Analysis of error masking and restoring properties of sequential circuits. IEEE Trans on Computer 62(9):1694–1704MathSciNetCrossRefzbMATHGoogle Scholar
  18. 18.
    Lin Y, He L (2007) Device and architecture concurrent optimization for FPGA transient soft error rate. In: Proc of IEEE/ACM International Conference on Computer-Aided Design, pp. 194–198Google Scholar
  19. 19.
    Liu BJ, Cai L (2012) Reliability evaluation for single event transients on digital circuits. IEEE Trans on Reliability 61(3):687–691CrossRefGoogle Scholar
  20. 20.
    Liu BJ, Cai L (2017) Monte Carlo reliability model for single-event transient on combinational circuits. IEEE Trans on Nuclear Science 64(12):2933–2937CrossRefGoogle Scholar
  21. 21.
    Mohammadi K, Jahanirad H, Attarsharghi P (2011) Fast reliability analysis method for sequential logic circuits. In: Proc. of 21st International Conference on Systems Engineering, pp. 352–356Google Scholar
  22. 22.
    Narasimham B (2007) Characterization of digital signal event transient pulse-widths in 130-nm and 90-nm CMOS technologies. IEEE Trans on Nuclear Science 54(6):2506–2510CrossRefGoogle Scholar
  23. 23.
    Naviner L, Liu KK, Cai H, Naviner JF (2014) Efficient computation of combinational circuits reliability based on probabilistic transfer matrix. In: Proc of IEEE International Conference on IC Design & Technology, pp. 1–4Google Scholar
  24. 24.
    Pahlevanzadeh H, Yu QY (2014) Systematic analyses for latching probability of single-event transients. In: Proc. of 15th International Symposium on Quality Electronic Design, pp. 442–449Google Scholar
  25. 25.
    Rao RR, Chopra K, Blaauw DT, Sylvester DM (2007) Computing the soft error rate of a combinational logic circuit using parameterized descriptors. IEEE Trans on Computer Aided Design of Integrated Circuits and Systems 26(3):468–479CrossRefGoogle Scholar
  26. 26.
    Reorda MS, Violante M (2004) A new approach to the analysis of single event transients in VLSI circuits. J Electron Test 20(5):511–521CrossRefGoogle Scholar
  27. 27.
    Salehi M, Azarpeyvand A, Aboutalebi AH (2018) Vulnerability analysis of adder architectures considering design and synthesis constraints. J Electron Test 34(1):7–14CrossRefGoogle Scholar
  28. 28.
    Salman E, Friedman EG (2010) Reducing delay uncertainty in deeply scaled integrated circuits using interdependent timing constraints. In: Proc. of IEEE proceedings of ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 1–6Google Scholar
  29. 29.
    Seifert N, Gill B, Jahinuzzaman S, Basile J (2012) Soft error susceptibilities of 22 nm tri-gate devices. IEEE Trans on Nuclear Science 59(6):2666–2673CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Hunan Provincial Key Laboratory of Intelligent Processing of Big Data on Transportation & School of Computer and Communication EngineeringChangsha University of Science and TechnologyChangshaChina

Personalised recommendations