Journal of Electronic Testing

, Volume 35, Issue 1, pp 77–85 | Cite as

Design of Two-Tone RF Generator for On-Chip IP3/IP2 Test

  • Shakeel AhmadEmail author
  • Jerzy Dąbrowski


In this paper a built-in-self-test (BiST) aimed at the third and second intercept point (IP3/IP2) characterization of RF receiver is discussed with a focus on a stimulus generator. The generator is designed based on a specialized phase-lock loop (PLL) architecture with two voltage controlled oscillators (VCOs) operating in GHz frequency range. The objective of PLL is to keep the VCOs’ frequency spacing under control. According to the test requirements the phase noise and nonlinear distortion of the two-tone generator are considered as a merit for the design of VCOs and analog adder. The PLL reference spurs, critical for the IP3 measurement, are avoided by means of a frequency doubling technique. The circuit is designed in 65 nm CMOS. A highly linear analog adder with OIP3 > +15 dBm and ring VCOs with phase noise < −104 dBc/Hz at 1 MHz offset are used to generate the RF stimulus of total power greater than −22 dBm. In simulations a performance sufficient for IP3/IP2 test of a typical RF CMOS receiver is demonstrated.


BiST IP3/IP2 test On-chip test Phase noise PLL Receiver front-end RF stimulus Two-tone generator 



  1. 1.
    Abidi AA (2006) Phase noise and jitter in CMOS ring oscillators. IEEE J Solid State Circuits 41(8):1803–1816CrossRefGoogle Scholar
  2. 2.
    Ahmad S et al (2010) Two-tone PLL for on-chip IP3 test. Proc. IEEE international symposium of circuits and systems (ISCAS) pp 3549–52Google Scholar
  3. 3.
    Badillo DA, Kiaei S (2004) Comparison of contemporary CMOS ring oscillators. Proc. IEEE Radio Frequency Integrated Circuits (RFIC) pp 281–284Google Scholar
  4. 4.
    Badillo DA, Kiaei S (2004) A low phase noise 2.0 V 900 MHz CMOS voltage controlled ring oscillator. Proc. IEEE International Symposium of Circuits and Systems (ISCAS) pp 533–536Google Scholar
  5. 5.
    Banerjee G, Behera M (2011) Signal generator for a built-in self test. U.S. Patent Publication No. US20110273197 A1Google Scholar
  6. 6.
    Banerjee G, Behera M, Zeidan MA, Chen R, Barnett K (2011) Analog/RF built-in-self-test subsystem for a mobile broadcast video receiver in 65-nm CMOS. IEEE J Solid State Circuits 46(9):1998–2008CrossRefGoogle Scholar
  7. 7.
    Bechthum E, Radulov GI, Briaire J, Geelen GJGM, van Roermund AHM (2016) A wideband RF mixing-DAC achieving IMD < −82 dBc up to 1.9 GHz. IEEE J Solid State Circuits 51(6):1374–1384CrossRefGoogle Scholar
  8. 8.
    Best RE (1993) Phase-locked loops, theory, design and applications. McGraw-Hill, New YorkGoogle Scholar
  9. 9.
    Bhansali P, Roychowdhury J (2009) Gen-Adler: The generalized Adler's equation for injection locking analysis in oscillators. Proc. IEEE Asia and South Pacific Design Automation (ASP-DAC) pp 522–527Google Scholar
  10. 10.
    Brandolini M, Rossi P, Manstretta D, Svelto F (2005) Toward multistandard mobile terminals — fully integrated receivers requirements and architectures. IEEE Trans Microwave Theory Tech 53(3):1026–1038CrossRefGoogle Scholar
  11. 11.
    Giannini V et al (2009) A 2mm2 0.1-to-5 GHz SDR receiver in 45nm digital CMOS. Proc. IEEE international solid-state circuits conference (ISSCC) pp 408–409Google Scholar
  12. 12.
    Kong L, Razavi B (2016) A 2.4 GHz 4 mW integer-N inductorless RF synthesizer. IEEE J Solid State Circuits 51(3):626–635CrossRefGoogle Scholar
  13. 13.
    Lin WT, Huang HY, Kuo TH (2014) A 12-bit 40 nm DAC achieving SFDR > 70 dB at 1.6 GS/s and IMD < −61 dB at 2.8 GS/s with DEMDRZ technique. IEEE J Solid State Circuits 49(3):708–717CrossRefGoogle Scholar
  14. 14.
    Mirzaei A, Darabi H (2014) Mutual pulling between two oscillators. IEEE J Solid State Circuits 49(2):360–372CrossRefGoogle Scholar
  15. 15.
    Radulov GI, Quinn PJ, van Roermund AHM (2015) A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC with signal-independent delta-I noise DfT scheme. IEEE Trans VLSI Syst 23(1):44–53CrossRefGoogle Scholar
  16. 16.
    Radulov GI, Quinn PJ, van Roermund AHM (2015) A 28-nm CMOS 7-GS/s 6-bit DAC with DfT clock and memory reaching SFDR >50 dB up to 1 GHz. IEEE Trans VLSI Syst 23(9):1941–1945CrossRefGoogle Scholar
  17. 17.
    Razavi B (1998) RF microelectronics. Prentice Hall, New Jersey, pp 11–25Google Scholar
  18. 18.
    Razavi B (1998) RF microelectronics. Prentice Hall, New Jersey, pp 270–277Google Scholar
  19. 19.
    Razavi B (2004) A study of injection locking and pulling in oscillators. IEEE J Solid State Circuits 39(9):1415–1424CrossRefGoogle Scholar
  20. 20.
    Razavi B (2007) Design of analog CMOS integrated circuits. McGraw-Hill, New York, pp 458–463Google Scholar
  21. 21.
    Shi C, Sánchez-Sinencio E (2017) On-chip two-tone synthesizer based on a mixing-FIR architecture. IEEE J Solid State Circuits 52(8):2105–2116CrossRefGoogle Scholar
  22. 22.
    Shi C et al (2011) −99dBc/Hz@10kHz 1MHz- step dual-loop integer-N PLL with anti-mislocking frequency calibration for global navigation satellite system receiver. Proc. IEEE International Symposium of Circuits and Systems (ISCAS) pp 1876–1879Google Scholar
  23. 23.
    Staszewski RB, Bashir I, Eliezer O (2007) RF built-in self test of a wireless transmitter. IEEE Trans Circuits Syst Express Briefs 54(2):186–190CrossRefGoogle Scholar

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© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Linköping UniversityLinköpingSweden
  2. 2.University of Management & TechnologyLahorePakistan

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