Journal of Electronic Testing

, Volume 35, Issue 1, pp 111–117 | Cite as

A Layout-Based Rad-Hard DICE Flip-Flop Design

  • Haibin WangEmail author
  • Xixi Dai
  • Younis Mohammed Younis Ibrahim
  • Hongwen Sun
  • Issam Nofal
  • Li Cai
  • Gang Guo
  • Zicai Shen
  • Li Chen


The DICE flip-flop has been rendered ineffective in deep-submicron technology nodes (e.g. 65 nm and 28 nm) due to charge sharing when exposed to single event strikes. This paper presents a new single event upset tolerant flip-flop design by applying the hardening technique on DICE at the layout level. This approach is an alternative to existing Layout Design through Error-Aware Transistor Positioning (LEAP); it also re-places transistors in master and slave DICE latches in the zigzag fashion in the layout. Both computer simulations and heavy-ion experimental results demonstrate that our proposed layout design has no single event upset errors under normal strikes until LET = 37 MeV·cm2/mg compared to the traditional DICE structure.


DICE LEAP DICE Rad-hard flip-flop Single event upset Charge sharing 



This work is supported by the Fundamental Research Funds for the Central Universities (2016B07414 & 2018B49614) and by the opening fund of Key Laboratory of Silicon Device Technology, Chinese Academy of Sciences. It is also supported through Innovation Foundation of Radiation Application, China Institute of Atomic Energy under contract No. KFZC2018040205.


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© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.College of IoT EngineeringHohai UniversityChangzhouChina
  2. 2.College of EngineeringUniversity of SaskatchewanSaskatoonCanada
  3. 3.Innovation Foundation of Radiation ApplicationChina Institute of Atomic EnergyBeijingChina
  4. 4.iRoC TechnologiesGrenobleFrance
  5. 5.Beijing Institute of Spacecraft Environment EngineeringBeijingChina

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