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Fault Leveling Techniques for Yield and Reliability Enhancement of NAND Flash Memories

  • Shyue-Kung Lu
  • Shang-Xiu Zhong
  • Masaki Hashizume
Article
  • 4 Downloads

Abstract

Novel fault leveling techniques based on address remapping (AR) are proposed in this paper. We can change the logical-to-physical address mapping of the page buffer such that faulty cells within a flash page can be evenly distributed into different codewords. Therefore, the adopted ECC scheme can correct them effectively. Based on the production test or on-line BIST results, the fault bitmap can be used for executing the heuristic fault leveling analysis (FLA) algorithm and evaluating control words used to steer fault leveling. A new page buffer architecture suitable for address remapping is also proposed. According to experimental results, repair rate, yield, and reliability can be improved significantly with negligible hardware overhead.

Keywords

Flash memory ECC Fault leveling Address remapping Reliability Yield 

References

  1. 1.
    Bez R, Camerlenghi E, Modelli A, Visconti A (2003) Introduction to flash memory. Proc IEEE 91(4):489–502CrossRefGoogle Scholar
  2. 2.
    Cao H, Huo ZL, Wang Y, Li T, Liu J, Jin L, Zhang D, Li D, Liu M (2014) A page buffer design based on stable and area-saving embedded SRAM for flash applications,” In Proc. IEEE Int’l Conf. on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1–3Google Scholar
  3. 3.
    Chen CW, Wu CW (2010) An adaptive code rate EDAC scheme for 16-bit random access memory. In Proc. Int’l Conf Design automation and Test in Europe (DATE). pp. 735–740Google Scholar
  4. 4.
    Gabrys R, Yaakobi E, Dolecek L (2012) Graded bit-error-correcting codes with applications to flash memory. IEEE Trans Inf Theory 59(4):2315–2327MathSciNetCrossRefGoogle Scholar
  5. 5.
    Ginez O, Portal JM, Aziza H (2008) Reliability issues in flash memories: an on-line diagnosis and repair scheme for word line drivers. In Proc. Int’l Workshop on Mixed-Signals, Sensors, and Systems Test, pp. 1–6Google Scholar
  6. 6.
    Ginez O, Portal JM, Aziza H (2009) An on-line testing scheme for repairing purposes in flash memories. In Proc. IEEE Int’l Symp Design and Diagnostics of Electronic Circuits & Systems (DDECS), pp 213–216Google Scholar
  7. 7.
    Hamming RW (1950) Error detecting and correcting codes. Bell Syst Tech J 29:147–160MathSciNetCrossRefGoogle Scholar
  8. 8.
    Ho CC, Liu YP, Chang YH, Kuo TW (2017) Anti-wear leveling design for SSDs with hybrid ECC capability. IEEE Trans VLSI Systems 25(2):488–501CrossRefGoogle Scholar
  9. 9.
    Hsiao YY, Chen CH, Wu CW (2006) A built-in self-repair scheme for NOR-type flash memory. Proc. IEEE VLSI Test Symp (VTS), Berkeley, pp. 114–119Google Scholar
  10. 10.
    Hsiao YY, Chen CH, Wu CW (2010) Built-in self-repair schemes for flash memories. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems 29(8):1243–1256CrossRefGoogle Scholar
  11. 11.
    Hsieh JW, Chen CW, Lin HY (2015) Adaptive ECC scheme for hybrid protection of SSD’s. IEEE Trans Comput 64(12):3348–3361MathSciNetCrossRefGoogle Scholar
  12. 12.
    Huang M, Xu B, Liu ZQ, Xu Y, Wu D (2017) Implicit programming: a fast programming strategy for NAND flash memory storage systems adopting redundancy methods. IEEE Embed Syst Lett 9(2):37–40CrossRefGoogle Scholar
  13. 13.
    Kang SM, Leblebici Y (2003) CMOS digital integrated circuits: analysis and design. New York :McGraw HillGoogle Scholar
  14. 14.
    Lin S, Costello DJ (2004) Error Control Coding, 2nd edn. Pearson Prentice Hall, Englewood CliffszbMATHGoogle Scholar
  15. 15.
    Lin YM, Li HT, Chung MH, Wu AY (2015) Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems. IEEE Trans Circuits and Systems I 62(7):1794–1804CrossRefGoogle Scholar
  16. 16.
    Micheloni R, Picca M, Amato S, Schwalm H, Scheppler M, Commodaro S (2009) Non-volatile memories for removable media. Proc IEEE 97(1):148–160CrossRefGoogle Scholar
  17. 17.
    Mielke NR, Frickey RE, Kalastirsky I, Quan M, Ustinov D, Vasudevan VJ (2017) Reliability of solid-state drives based on NAND flash memory. Proc IEEE 105(9):1725–1750CrossRefGoogle Scholar
  18. 18.
    Mohammad MG, Saluja KK (2001) Flash memory disturbances: modeling and test. In Proc. IEEE VLSI Test Symp (VTS), pp. 218–224Google Scholar
  19. 19.
    Park Y, Lee J, Cho SS, Jin G, Jung E (2014) Scaling and reliability of NAND flash devices. In Proc IEEE 52nd Int Reliab Phys Symp (IRPS), pp. 2E.1.1-2E.1.4Google Scholar
  20. 20.
    Pavan P, Bez R, Olivo P, Zanoni E (1997) Flash memory cells. Proc IEEE 85(8):1248–1271CrossRefGoogle Scholar
  21. 21.
    Sala F, Kees A, Schouhamer Immink A, Dolecek L (2015) Error control schemes for modern flash memories. IEEE Consumer Electronics Magazine 4:66–73CrossRefGoogle Scholar
  22. 22.
    Shin D, Park J, Park J, Paul S, Bhunia S (2017) Adaptive ECC for Tailored Protection of Nanoscale Memory. IEEE Design and Test of Computers 34(6):84–93CrossRefGoogle Scholar
  23. 23.
    Wang Y, Huang M, Shao Z, Chan HCB, Bathen LAD, Dutt ND (2014) A Reliability-Aware Address Mapping Strategy for NAND Flash Memory Storage Systems. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems 33(11):1623–1631CrossRefGoogle Scholar
  24. 24.
    Wang Y, Qin Z, Chen R, Shao Z, Wang Q, Li S, Yang LT (2016) A Real-Time Flash Translation Layer for NAND Flash Memory Storage Systems. IEEE Trans Multi-Scale Computing Systems 2(1):17–29CrossRefGoogle Scholar
  25. 25.
    Wang S, Wu F, Lu Z, Zhou Y, Xiong Q, Zhang M, Xie C (2017) Lifetime adaptive ECC in NAND flash page management. In Proc. IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1253-1256Google Scholar
  26. 26.
    Wei D, Deng L, Zhang P, Qiao L, Peng X (2016) NRC: A Nibble Remapping Coding Strategy for NAND Flash Reliability Extension. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems 35(11):1942–1946CrossRefGoogle Scholar
  27. 27.
    Yang CG, Emre Y, Chakrabarti C (2012) Product code schemes for error correction in MLC NAND flash memories. IEEE Trans VLSI Systems 20(12):2302–2314CrossRefGoogle Scholar
  28. 28.
    Yang MC, Chang YM, Tsao CW, Huang PC, Chang YH, Kuo TW, (2014) Garbage collection and wear leveling for flash memory: Past and future. In Proc Int’l Conf on Smart Computing, pp. 66–73Google Scholar
  29. 29.
    Yeh JC, Cheng KL, Chou YF, Wu CW (2007) Flash memory testing and built-in self-diagnosis with march-like test algorithms. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems 26(6):1101–1113CrossRefGoogle Scholar
  30. 30.
    Zhao K, Zhao W, Sun H, Zhang T, Zhang X, Zheng N (2013) LDPC in-SSD: making advanced error correction codes work effectively in solid state drives. In FAST ’13Google Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Electrical EngineeringNational Taiwan University of Science and TechnologyTaipeiTaiwan
  2. 2.Institute of Technology and ScienceTokushima UniversityTokushimaJapan

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