Journal of Electronic Testing

, Volume 34, Issue 5, pp 559–570 | Cite as

Fault Leveling Techniques for Yield and Reliability Enhancement of NAND Flash Memories

  • Shyue-Kung LuEmail author
  • Shang-Xiu Zhong
  • Masaki Hashizume


Novel fault leveling techniques based on address remapping (AR) are proposed in this paper. We can change the logical-to-physical address mapping of the page buffer such that faulty cells within a flash page can be evenly distributed into different codewords. Therefore, the adopted ECC scheme can correct them effectively. Based on the production test or on-line BIST results, the fault bitmap can be used for executing the heuristic fault leveling analysis (FLA) algorithm and evaluating control words used to steer fault leveling. A new page buffer architecture suitable for address remapping is also proposed. According to experimental results, repair rate, yield, and reliability can be improved significantly with negligible hardware overhead.


Flash memory ECC Fault leveling Address remapping Reliability Yield 


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© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Electrical EngineeringNational Taiwan University of Science and TechnologyTaipeiTaiwan
  2. 2.Institute of Technology and ScienceTokushima UniversityTokushimaJapan

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