Dynamic Analog/RF Alternate Test Strategies Based on On-chip Learning

  • Parth Kansara
  • Sharanabasavaraja Bheema Reddy
  • Louay Abdallah
  • Ke Huang
Article
  • 8 Downloads

Abstract

Analog/RF alternate test schemes have been extensively studied in the past decade with the goal of replacing time-consuming and expensive specification tests with low-cost alternate measurements. A common approach in analog/RF alternate test is to build non-linear regression models to map the specification tests to alternate measurements, or to learn a pass/fail separation boundary directly in the space of alternate measurements. Among various challenges that have been discussed in alternate test, the model stationarity is a major bottle-neck that prevents test engineers from deploying it in long-term applications. In this work, we show that alternate test strategies can be implemented on-chip using analog/RF Built-In Self-Test (BIST) circuitry. Moreover, model refinement and dynamic adaptation can be achieved based on an automatic on-chip learning structure. Effectiveness of the proposed approach is demonstrated using experimental results from an RF Low Noise Amplifier (LNA) and its BIST implementation.

Keywords

Analog/RF testing Alternate test On-chip learning 

References

  1. 1.
    Akbay S, Halder A, Chatterjee A, Keezer D (2004) Low-cost test of embedded RF/analog/mixed-signal circuits in SOPs. IEEE Trans Adv Packag 27(2):352–363CrossRefGoogle Scholar
  2. 2.
    Andraud M, Stratigopoulos HG, Simeu E (2016) One-shot non-intrusive calibration against process variations for analog/RF circuits. IEEE Trans Circuits Syst Regul Pap 63(11):2022–2035CrossRefGoogle Scholar
  3. 3.
    Ayari H, Azais F, Bernard S, Comte M, Kerzerho V, Potin O, Renovell M (2012) Making predictive analog/RF alternate test strategy independent of training set size. In: Proc. IEEE International Test Conference. Paper 10.1Google Scholar
  4. 4.
    Biswas S, Blanton RD (2008) Test compaction for mixed-signal circuits using pass-fail test data. In: IEEE VLSI Test Symposium, pp 299–308Google Scholar
  5. 5.
    Brockman JB, Director SW (1989) Predictive subset testing: Optimizing IC parametric performance testing for quality, cost, and yield. IEEE Trans Semicond Manuf 2(3):104–113CrossRefGoogle Scholar
  6. 6.
    Cimino M, Lapuyade H, Matos MD, Taris T, Deval Y, Begueret J (2006) A robust 130nm-CMOS built-in current sensor dedicated to RF applications. In: IEEE European Test Symposium, pp 151–158Google Scholar
  7. 7.
    da Silva JM (2006) A low-power oscillation based LNA BIST scheme. In: International Conference on Design and Test of Integrated Systems in Nanoscale Technology, pp 268–272Google Scholar
  8. 8.
    Dermentzoglou L, Arapoyanni A, Tsiatouhas Y (2010) A built-in test circuit for RF differential low noise amplifiers. IEEE Trans Circuits Syst Regul Pap 57(7):1549–1558MathSciNetCrossRefGoogle Scholar
  9. 9.
    Han D, Kim BS, Chatterjee A (2010) DSP-Driven self-tuning of RF circuits for process-induced performance variability. IEEE Transactions on VLSI Systems 18(2):305–314CrossRefGoogle Scholar
  10. 10.
    Huang K, Kupp N, Carulli J, Makris Y (2013) Handling discontinuous effects in modeling spatial correlation of wafer-level analog/RF tests. In: Design, Automation and Test in Europe Conference (DATE), pp 553–558Google Scholar
  11. 11.
    Huang K, Stratigopoulos HG, Abdallah L, Mir S, Bounceur A (2013) Multivariate statistical techniques for analog parametric test metrics estimation. In: IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), pp 6–11Google Scholar
  12. 12.
    Huang K, Kupp N, Xanthopoulos C, Carulli J, Makris Y (2015) Low-cost analog/RF IC testing through combined intra- and inter-die correlation models. IEEE Des Test 32(1):53–60Google Scholar
  13. 13.
    Huang K, Wen J, Willmore J (2016) Test suite-based analog/RF test time reduction using canonical correlation. IEEE Trans Comput Aided Des Integr Circuits Syst 35(12):2143–2147CrossRefGoogle Scholar
  14. 14.
    Huss SD, Gyurcsik RS (1991) Optimal ordering of analog integrated circuit tests to minimize test time. In: ACM/IEEE Design Automation Conference, pp 494–499Google Scholar
  15. 15.
    Kupp N, Huang K, Carulli J, Makris Y (2012) Spatial correlation modeling for probe test cost reduction. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)Google Scholar
  16. 16.
    Liu F (2007) A general framework for spatial correlation modeling in VLSI design. In: Design Automation Conference, pp 817– 822Google Scholar
  17. 17.
    Maeda Y, Wakamura M (2005) Simultaneous perturbation learning rule for recurrent neural networks and its fpga implementation. IEEE Trans Neural Netw 16(6):1664–1672CrossRefGoogle Scholar
  18. 18.
    Milor L, Sangiovanni-Vincentelli AL (1994) Minimizing production test time to detect faults in analog circuits. IEEE Trans Comput Aided Des Integr Circuits Syst 13(6):796–813CrossRefGoogle Scholar
  19. 19.
    Spall J (1998) Implementation of the simultaneous perturbation algorithm for stochastic optimization. IEEE Trans Aerosp Electron Syst 34(3):817–823CrossRefGoogle Scholar
  20. 20.
    Stratigopoulos HG, Makris Y (2008) Error moderation in low-cost machine-learning-based analog/RF testing. IEEE Trans Comput Aided Des Integr Circuits Syst 27(2):339–351CrossRefGoogle Scholar
  21. 21.
    Stratigopoulos HG, Mir S, Bounceur A (2009) Evaluation of analog/RF test measurements at the design stage. IEEE Trans Comput Aided Des Integr Circuits Syst 28(4):582–590CrossRefGoogle Scholar
  22. 22.
    Stratigopoulos HG, Drineas P, Slamani M, Makris Y (2010) RF Specification test compaction using learning machines. IEEE Trans Very Large Scale Integr VLSI Syst 18(6):998–1002CrossRefGoogle Scholar
  23. 23.
    Valdes-Garcia A, Silva-Martinez J, Sanchez-Sinencio E (2006) On-chip testing techniques for rf wireless transceivers. IEEE Des Test Comput 23(4):268–277CrossRefGoogle Scholar
  24. 24.
    Variyam PN, Cherubal S, Chatterjee A (2002) Prediction of analog performance parameters using fast transient testing. IEEE Trans Comput Aided Des Integr Circuits Syst 21(3):349–361CrossRefGoogle Scholar
  25. 25.
    Volanis G, Maliuk D, Lu Y, Subramani K, Antonopoulos A, Makris Y (2016) On-die learning-based self-calibration of analog/RF ICs. In: IEEE VLSI Test Symposium, pp 1–6Google Scholar
  26. 26.
    Voorakaranam R, Akbay SS, Bhattacharya S, Cherubal S, Chatterjee A (2007) Signature testing of analog and RF circuits: Algorithms and methodology. IEEE Trans Circuits Syst I 54(5):1018–1031CrossRefGoogle Scholar
  27. 27.
    Zhang W, Li X, Liu F, Acar E, Rutenbar R, Blanton R (2011) Virtual probe: a statistical framework for low-cost silicon characterization of nanoscale integrated circuits. IEEE Trans Comput Aided Des Integr Circuits Syst 30(12):1814–1827CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Electrical and Computer EngineeringSan Diego State UniversitySan DiegoUSA
  2. 2.Dolphin IntegrationMeylan CedexFrance

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