With the application of heterogeneous integration and advanced packaging technologies, the use of through-silicon vias (TSVs) to deliver the power supply has become popular in the design of stacked chips in three-dimensional integrated circuits. High-density vertical interconnections offer higher speed and bandwidth, but the electromagnetic coupling effect among TSVs becomes more serious. Therefore, investigation of the noise coupling among TSVs and analysis of its impact on the power supply become important considerations. An analytical model based on the theory of multiconductor transmission lines (MTLs) is presented herein to discuss such TSV noise coupling. The method can accurately and quickly estimate the noise coupling coefficient among a large number of TSVs and offers good practicability for similar structures and even the TSVs of complex structures. Further, the influence of TSV noise coupling and simultaneous switching noise from switching circuits on the supplied power voltage is discussed. Finally, the parameters of an actual Intel chip are taken as an example to analyze the supplied power voltage that reaches complementary metal–oxide–semiconductor (CMOS) circuits through the three-dimensional (3D) power distribution network after considering the power supply noise. The presented model is validated by comparing the calculation results with those obtained from a full-wave simulator. The runtime and memory consumption requirements are lower than those of the full-wave simulator.
This is a preview of subscription content, log in to check access.
Buy single article
Instant access to the full article PDF.
Price includes VAT for USA
Subscribe to journal
Immediate online access to all issues from 2019. Subscription will auto renew annually.
This is the net price. Taxes to be calculated in checkout.
Papanikolaou, A., Soudris, D., Radojcic, R.: Three Dimensional System Integration. Springer, Boston (2011)
Shen, W., Lin, Y., Chen, S., Chang, H., Chang, T., Lo, W., Lin, C., Chou, Y., Kwai, D., Kao, M., Chen, K.: 3-D stacked technology of DRAM-logic controller using through-silicon via (TSV). IEEE J. Electron Devices Soc. 6, 396–402 (2018)
Thadesar, P.A., Gu, X., Alapati, R., Bakir, M.S.: Through-silicon vias: drivers, performance, and innovations. IEEE Trans. Compon. Packag. Manuf. Technol. 6(7), 1007–1017 (2016)
Kim, J., Pak, J.S., Cho, J., Song, E., Cho, J., Kim, H., Song, T., Lee, J., Lee, H., Park, K.: High-frequency scalable electrical model and analysis of a through silicon via (TSV). IEEE Trans. Compon. Packag. Manuf. Technol. 1(2), 181–195 (2011)
Pizzagalli, A., Buisson, T., Beica, R.: 3D technology applications market trends & key challenges. In: 25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014), Saratoga Springs, NY, pp. 78–81 (2014)
Wang, F., Yu, N.: An effective approach of improving electrical and thermo-mechanical reliabilities of through-silicon vias. IEEE Trans. Device Mater. Reliab. 17(1), 106–112 (2017)
Qu, C., Ding, R., Liu, X., Zhu, Z.: Modeling and optimization of multiground TSVs for signals shield in 3-D ICs. IEEE Trans. Electromagn. Compat. 59(2), 461–467 (2017)
Vaisband, B., Friedman, E.G.: Noise coupling models in heterogeneous 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. 24(8), 1–9 (2016)
Xu, H., Pavlidis, V.F., Micheli, G.D.: Analytical heat transfer model for thermal through-silicon vias. In: 2011 Design, Automation & Test in Europe, Grenoble, pp. 1–6 (2011)
Lim, J., Cho, J., Jung, D.H., Kim, J.J., Choi, S., Kim, D., Lee, M., Kim, J.: Modeling and analysis of TSV noise coupling effects on RF LC-VCO and shielding structures in 3D IC. IEEE Trans. Electromagn. Compat. 60(6), 1939–1947 (2018)
He, H., Lu, J.Q.: Modeling and analysis of PDN impedance and switching noise in TSV-based 3-D integration. IEEE Trans. Electron Devices 62(4), 1241–1247 (2015)
Xu, C., Suaya, R., Banerjee, K.: Compact modeling and analysis of through-si-via-induced electrical noise coupling in three-dimensional ICs. IEEE Trans. Electron Devices 58(11), 4024–4034 (2011)
Peng, Y., Song, T., Petranovic, D., Lim, S.K.: Silicon effect-aware full-chip extraction and mitigation of TSV-to-TSV coupling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12), 1900–1913 (2014)
Serafy, C., Srivastava, A.: TSV replacement and shield insertion for TSV–TSV coupling reduction in 3-D global placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4), 554–562 (2015)
Cho, J., Song, E., Yoon, K., Pak, J.S., Kim, J., Lee, W., Song, T., Kim, K., Lee, J., Lee, H.: Modeling and analysis of through-silicon via (TSV) noise coupling and suppression using a guard ring. IEEE Trans. Compon. Packag. Manuf. Technol. 1(2), 220–233 (2011)
Otsuka, H., Kubo, G., Kobayashi, R., Mido, T., Sudo, T.: On-die PDN design and analysis for minimizing power supply noise. In: 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), Taipei, pp. 17–20 (2015)
Kim, K., Lee, W., Kim, J., Song, T., Kwon, Y.: Analysis of power distribution network in TSV-based 3D-IC. In: 19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems, Austin, TX, pp. 177–180 (2010)
Xu, Z., Wu, Q., He, H., Lu, J.Q.: Electromagnetic-simulation program with integrated circuit emphasis modeling, analysis, and design of 3-D power delivery. IEEE Trans. Compon. Packag. Manuf. Technol. 3(4), 641–652 (2013)
Pak, J.S., Kim, J., Cho, J., Kim, K., Song, T., Ahn, S., Lee, J., Lee, H., Park, K., Kim, J.: PDN impedance modeling and analysis of 3D TSV IC by using proposed P/G TSV array model based on separated P/G TSV and chip-PDN models. IEEE Trans. Compon. Packag. Manuf. Technol. 1(2), 208–219 (2011)
He H., Lu J.Q., Gu X.: Analysis of TSV geometric parameter impact on switching noise in 3D power distribution network. In: 25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014), Saratoga Springs, NY, pp. 67–72 (2014)
He, H., Lu, J.Q., Zheng, X., Gu, X.: TSV density impact on 3D power delivery with high aspect ratio TSVs. In: ASMC 2013 SEMI Advanced Semiconductor Manufacturing Conference, Saratoga Springs, NY, pp. 70–74 (2013)
Paul, C.R.: Analysis of Multiconductor Transmission Lines. Wiley, New York (2008)
Gu, X., Silberman, J.A., Young, A.M., Jenkins, K.A., Bing, D., Yong, L., Duan, X., Gordin, R., Shlafman, S., Goren, D.: Characterization of TSV-induced loss and substrate noise coupling in advanced three-dimensional CMOS SOI technology. IEEE Trans. Compon. Packag. Manuf. Technol. 3(11), 1917–1925 (2013)
Ye, H.Q., Wei, X.C., Li, E.P.: A novel semi-analytical solution of impedance of grid-type power distribution network. In: 2015 IEEE International Symposium on Electromagnetic Compatibility (EMC), Dresden, pp. 606–611 (2015)
Ding, W.Y., Wei, X.C., Yi, D., Shu, Y.F.: A closed-form solution for the impedance calculation of grid power distribution network. IEEE Trans. Electromagn. Compat. 59(5), 1449–1456 (2017)
Intel core i7-980x processor. https://www.intel.com/content/www/us/en/products/processors/core/i7-processors.html (2018). Accessed 21 June 2018
This research was supported in part by the National Natural Science Foundation of China (grant nos. 61574106 and 61574104), in part by the National Defense Pre-Research Foundation of China (grant no. 9140A23060115DZ01062), and in part by the Key Science and Technology Special Project of Shaanxi Province (grant no. 2015KTCQ01-5).
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
About this article
Cite this article
Zhu, W., Wang, Y., Dong, G. et al. MTL-based modeling and analysis of the effects of TSV noise coupling on the power delivery network in 3D ICs. J Comput Electron (2020). https://doi.org/10.1007/s10825-020-01466-w
- 3D IC
- Through-silicon via (TSV)
- Noise coupling
- Multiconductor transmission lines (MTLs)
- Power delivery network (PDN)
- Power supply noise (PSN)
- Simultaneous switching noise (SSN)