Journal of Computational Electronics

, Volume 18, Issue 4, pp 1201–1206 | Cite as

A fair comparison of the performance of charge plasma and electrostatic tunnel FETs for low-power high-frequency applications

  • Bandi Venkata ChandanEmail author
  • Kaushal Nigam
  • Chithraja Rajan
  • Dheeraj Sharma


A comparative investigation has been carried out on the charge plasma tunnel field-effect transistor (CP-TFET) and electrically doped TFET (ED-TFET). Both device structures are created on intrinsic silicon, but differ regarding the method employed to induce charge carriers in the intrinsic silicon area. In the charge plasma TFET, metal work function engineering is employed, while in the case of the ED-TFET, electrostatics is used to induce charge carriers at the drain/source side, resulting in the formation of n+ drain and p+ source regions. Both devices are analyzed for the same OFF-state current, which will reduce the gate leakage and enable a fair comparison of the devices. The analysis is carried out in terms of direct-current (DC) characteristics as well as analog and radiofrequency parameters, revealing that the charge plasma TFET exhibits better DC and analog/RF characteristics as compared with the electrically doped TFET. This occurs due to the lower work function applied at the source–channel region in the CP-TFET compared with the ED-TFET.


TFET Charge plasma Electrically doped Analog Radiofrequency 



  1. 1.
    Ionescu, A.M., Riel, H.: Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479(7373), 329–337 (2010)CrossRefGoogle Scholar
  2. 2.
    Choi, W.Y., Park, B.-G., Lee, J.D., Liu, T.-J.K.: Tunneling field-effect transistor (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28(8), 743–745 (2007)CrossRefGoogle Scholar
  3. 3.
    Koswatta, S.O., Lundstrom, M.S., Nikonov, D.E.: Performance comparison between p–i–n tunneling transistors and conventional MOSFETs. IEEE Trans. Electron Devices 56(3), 456–465 (2007)CrossRefGoogle Scholar
  4. 4.
    Damrongplasit, N., Shin, C., Kim, S.H., Vega, R.A., Liu, T.J.K.: Study of random dopant fluctuation effects in germanium-source tunnel FETs. IEEE Trans. Electron Devices 58(10), 3541–3548 (2011)CrossRefGoogle Scholar
  5. 5.
    Chiang, M.-H., Lin, J.-N., Kim, K., Chuang, C.-T.: Random dopant fluctuation in limited-width FinFET technologies. IEEE Trans. Electron Devices 54(8), 2055–2060 (2007)CrossRefGoogle Scholar
  6. 6.
    Royer, C.L., Mayer, F.: Exhaustive experimental study of tunnel field effect transistors (TFETs): from materials to architecture. In: Proceedings 10th International Conference on Ultimate Integration of Silicon, pp. 53–56. (2009)Google Scholar
  7. 7.
    Ghosh, B., Akram, M.W.: Junctionless tunnel field effect transistor. IEEE Electron Device Lett. 34(5), 584–586 (2013)CrossRefGoogle Scholar
  8. 8.
    Nadda, K., Kumar, M.J.: Thin-film bipolar transistors on recrystallized polycrystalline silicon without impurity doped junctions: proposal and investigation. J. Display Technol. 10(7), 590–594 (2014)CrossRefGoogle Scholar
  9. 9.
    Kumar, M.J., Nadda, K.: Bipolar charge-plasma transistor: a novel three terminal device. IEEE Trans. Electron Devices 59(4), 962–967 (2012)CrossRefGoogle Scholar
  10. 10.
    Kumar, M.J., Janardhanan, S.: Doping-less tunnel field effect transistor: design and investigation. IEEE Trans. Electron Devices 16(10), 3285–3290 (2013)CrossRefGoogle Scholar
  11. 11.
    Boucart, K., Ionescu, A.M.: Double-gate tunnel FET with high-k gate dielectric. IEEE Trans. Electron Devices 54(7), 1725–1733 (2007)CrossRefGoogle Scholar
  12. 12.
    Raad, B.R., Sharma, D., Kondekar, P.: Dual workfunction tunnel field-effect transistor with shifted gate for ambipolar suppression and ON current improvement. In: IEEE, ICCTICT. (2016)Google Scholar
  13. 13.
    Chandan, B.V., Dasari, S., Yadav, S., Sharma, D.: Approach to suppress ambipolarity and improve RF and linearity performances on ED-tunnel FET. IET Micro Nano Lett. 13, 684–689 (2018)CrossRefGoogle Scholar
  14. 14.
    Nigam, K., Kondekar, P., Sharma, D.: DC characteristics and analog/RF performance of novel polarity control GaAs-Ge based tunnel field effect transistor. Superlattices Microstruct. 92, 224–231 (2016)CrossRefGoogle Scholar
  15. 15.
    Lahgere, A., Sahu, C., Singh, J.: PVT-aware design of dopingless dynamically configurable tunnel FET. IEEE Trans. Electron Devices 62(8), 2404–2409 (2015)CrossRefGoogle Scholar
  16. 16.
    Lahgere, A., Sahu, C., Singh, J.: Electrically doped dynamically configurable field-effect transistor for low-power and high-performance applications. Electron. Lett. 51(16), 1284–1286 (2015)CrossRefGoogle Scholar
  17. 17.
    ATLAS Device Simulation Software, Silvaco Int., Santa Clara, CA, USA (2016)Google Scholar
  18. 18.
    Nigam, K., Kondekar, P., Sharma, D.: Approach for ambipolar behaviour suppression in tunnel FET by workfunction engineering. Micro Nano Lett. 11(8), 460–464 (2016)CrossRefGoogle Scholar
  19. 19.
    Rajasekharan, B., Hueting, R.J.E., Salm, C., Van Hemert, T., Wolters, R.A.M., Schmitz, J.: Fabrication and characterization of the charge plasma diode. IEEE Electron Device Lett. 31(6), 528–530 (2010)CrossRefGoogle Scholar
  20. 20.
    Nadda, K., Kumar, M.J.: Schottky collector bipolar transistor without impurity doped emitter and base: and performance. IEEE Trans. Electron Devices 60(9), 2956–2959 (2013)CrossRefGoogle Scholar
  21. 21.
    Teh, W.H., Rigg, A., Tung, C.H., Kumar, R., Balasubramanian, N., Kwong, D.L.: 200 mm wafer-scale epitaxial transfer of single crystal Si on glass by anodic bonding of silicon-on-insulator wafers. Appl. Phys. Lett. 87(7), 073107 (2005)CrossRefGoogle Scholar
  22. 22.
    Kima, H.S., Blick, R.K., Kim, D.M., Eom, C.B.: Bonding silicon-on-insulator to glass wafers for integrated bio-electronic circuits. Phys. Lett. 85(12), 2370–2372 (2004)Google Scholar
  23. 23.
    Zervas, M., Sacchetto, D., De Micheli, G., Leblebici, Y.: Top down fabrication of very-high density vertically stacked silicon nanowire arrays with low temperature budget. Microelectron. Eng. 88(10), 3127–3132 (2011)Google Scholar
  24. 24.
    De Marchi, M., et al.: Polarity control in double-gate, gate-all-round vertically stacked silicon nanowire FETs. In: IEDM Technical Devices, pp. 8.4.1–8.4.4 (2012)Google Scholar
  25. 25.
    Kim, K., Fossum, J.: Double-gate CMOS: symmetrical- versus asymmetrical-gate devices. IEEE Trans. Electron Devices 48(2), 294–299 (2001)CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  • Bandi Venkata Chandan
    • 1
    Email author
  • Kaushal Nigam
    • 2
  • Chithraja Rajan
    • 1
  • Dheeraj Sharma
    • 1
  1. 1.PDPM-India Institute of Information Technology Design and ManufacturingJabalpurIndia
  2. 2.Jaypee Institute of Information TechnologyNoidaIndia

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