Electrostatically doped drain junctionless transistor for low-power applications

  • Mohd Adil RaushanEmail author
  • Naushad Alam
  • Mohd Jawaid Siddiqui


Junctionless transistors (JLT) are a promising alternative to address the stringent junction requirements in conventional transistors. However, JLTs are plagued by high OFF-state leakage current attributed to the band-to-band tunneling at the channel–drain interface. This leakage current is often referred to as gate-induced drain leakage (GIDL). In this paper, we propose an effective technique to suppress GIDL in JLTs. We use the charge plasma concept to realize an electrostatically doped drain (EDD) separated from the channel by an intermediate intrinsic region. Therefore, the proposed EDD–JLT is an n+–n+–i–n+ structure that widens the tunnel barrier at the gate–drain interface in the OFF-state (VGS = 0 V, VDS = 1 V) and offers significant reduction in leakage current. We compare, using 2D TCAD device simulations, the EDD–JLT with the conventional JLT in terms of various digital and analog performance metrics. We observe that EDD–JLTs of gate length 20 nm offer a significant reduction in IOFF (~ 4 orders) while substantially improving ION/IOFF ratio (~ 4 orders) as compared to conventional JLTs. To study the scalability of the proposed technique, the device thickness and gate length were scaled down to 5 nm. We observe that even for scaled-down structure, EDD–JLTs retain their performance benefit. We observe that the analog performance metrics such as intrinsic gain (GmRo), transconductance generation factor (Gm/ID), output conductance (GD), channel length modulation, and drain-induced barrier lowering of EDD–JLTs are also significantly improved as compared to conventional JLTs.


Junctionless transistor Charge plasma Dopingless Band-to-band tunneling Leakage current 



This work was carried out under the project of “Visvesvaraya PhD Scheme for Electronics and IT” at Aligarh Muslim University, by Media Lab Asia (A Section 25 Company of Department of Electronics and Information Technology, Ministry of Communications and Information Technology, Govt. of India). The revised Implementation Order No. is “PhD-MLA/4(39)/2015-16/Dated 30.05.2016.” The authors are also thankful to the UGC of India for DSA-I grant and Start-Up grant.


  1. 1.
    Colinge, J.-P., Lee, C.-W., Afzalian, A., Akhavan, N.D., Yan, R., Ferain, I., Razavi, P., O’Neill, B., Blake, A., White, M., Kelleher, A.-M., McCarthy, B., Murphy, R.: Nanowire transistors without junctions. Nat. Nanotechnol. 5(3), 225–229 (2010)CrossRefGoogle Scholar
  2. 2.
    Choi, S.J., Il Moon, D., Kim, S., Duarte, J.P., Choi, Y.K.: Sensitivity of threshold voltage to nanowire width variation in junctionless transistors. IEEE Electron Device Lett. 32(2), 125–127 (2011)CrossRefGoogle Scholar
  3. 3.
    Gupta, G., Rajasekharan, B., Hueting, R.J.E., Member, S.: Electrostatic doping in semiconductor devices. IEEE Trans. Electron Devices 64(8), 3044–3055 (2017). CrossRefGoogle Scholar
  4. 4.
    Ramaswamy, S., Kumar, M.J.: Raised source/drain dopingless junctionless accumulation mode FET: design and analysis. IEEE Trans. Electron Devices 63(11), 4185–4190 (2016). CrossRefGoogle Scholar
  5. 5.
    Sahu, C., Singh, J.: Charge-plasma based process variation immune junctionless transistor. IEEE Electron Device Lett. 35(3), 411–413 (2014). CrossRefGoogle Scholar
  6. 6.
    Hur, J., Moon, D., Han, J., Kim, G., Jeon, C., Choi, Y.: Tunneling effects in a charge-plasma dopingless transistor. IEEE Trans. Electron Devices 16(2), 315–320 (2017). Google Scholar
  7. 7.
    Gundapaneni, S., Bajaj, M., Pandey, R.K., Murali, K.V.R.M., Ganguly, S., Kottantharayil, A.: Effect of band-to-band tunneling on junctionless transistors. IEEE Trans. Electron Devices 59(4), 1023–1029 (2012). CrossRefGoogle Scholar
  8. 8.
    Kumar, M.J., Sahay, S.: Controlling BTBT-induced parasitic BJT action in junctionless FETs using a hybrid channel. IEEE Trans. Electron Devices 63(8), 3350–3353 (2016). CrossRefGoogle Scholar
  9. 9.
    Sahay, S., Kumar, M.J.: Physical insights into the nature of gate-induced drain leakage in ultrashort channel nanowire FETs. IEEE Trans. Electron Devices 64(6), 2604–2610 (2017). CrossRefGoogle Scholar
  10. 10.
    Sahay, S., Kumar, M.J.: A novel gate-stack-engineered nanowire FET for scaling to the sub-10-nm regime. IEEE Trans. Electron Devices 63(12), 5055–5059 (2016). CrossRefGoogle Scholar
  11. 11.
    Ehteshamuddin, M., Loan, S.A., Rafat, M.: Planar junctionless silicon-on-insulator transistor with buried metal layer. IEEE Electron Device Lett. 39(6), 799–802 (2018). CrossRefGoogle Scholar
  12. 12.
    Sahay, S., Kumar, M.J.: Insight into lateral band-to-band-tunneling in nanowire junctionless FETs. IEEE Trans. Electron Devices 63(10), 4138–4142 (2016). CrossRefGoogle Scholar
  13. 13.
    Shan, C., Wang, Y., Bao, M.T.: A charge-plasma-based transistor with induced graded channel for enhanced analog performance. IEEE Trans. Electron Devices 63(6), 2275–2281 (2016). CrossRefGoogle Scholar
  14. 14.
    Gnudi, A., Reggiani, S., Gnani, E., Baccarani, G.: Analysis of threshold voltage variability due to random dopant fluctuations in junctionless FETs. IEEE Electron Device Lett. 33(3), 336–338 (2012). CrossRefGoogle Scholar
  15. 15.
    Atlas User’s Manual (2013) Silvaco, Santa Clara, CA, USAGoogle Scholar
  16. 16.
    Hänsch, W., Vogelsang, T., Kircher, R., Orlowski, M.: Carrier transport near the Si/SiO2 interface of a MOSFET. Solid State Electron. 32(10), 839–849 (1989). CrossRefGoogle Scholar
  17. 17.
    Raushan, M.A., Alam, N., Siddiqui, M.J.: Dopingless tunnel field-effect transistor with oversized back gate: proposal and investigation. IEEE Trans. Electron Devices 65(10), 4701–4708 (2018). CrossRefGoogle Scholar
  18. 18.
    Baruah, R.K., Paily, R.P.: A dual-material gate junctionless transistor with high-k spacer for enhanced analog performance. IEEE Trans. Electron Devices 61(1), 123–128 (2014). CrossRefGoogle Scholar
  19. 19.
    Gundapaneni, S., Ganguly, S., Kottantharayil, A.: Enhanced electrostatic integrity of short-channel junctionless transistor with high-k spacers. IEEE Electron Device Lett. 32(10), 1325–1327 (2011). CrossRefGoogle Scholar
  20. 20.
    Razavieh, A., Deng, Y., Zeitzoff, P., Na, M.H., Frougier, J., Karve, G., Brown, D.E., Yamashita, T, Nowak, E.J.: Effective drive current in scaled FinFET and NSFET CMOS inverters. In: 76th Device Research Conference (DRC) no. June 2018, 230–231 (2018). doi:

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Electronics Engineering Department, ZHCETAMUAligarhIndia

Personalised recommendations