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EMA-based modeling of the surface potential and drain current of dual-material gate-all-around TFETs

  • Varun Mishra
  • Yogesh Kumar Verma
  • Prateek Kishor Verma
  • Santosh Kumar Gupta
Article
  • 29 Downloads

Abstract

An analytical model for the surface potential and drain current of dual-material gate-all-around tunnel field-effect transistors based on evanescent mode analysis (EMA) is introduced. In the EMA, the channel potential is a sum of the solutions of the one-dimensional (1D) Poisson equation and two-dimensional (2D) Laplace equation. The EMA is preferred over the parabolic approximation due to the invariance of the characteristic length (λ) over the channel. The band-to-band tunneling rate is integrated over the tunneling volume to calculate the drain current. The accuracy of the model is evaluated by comparing it with results obtained from numerical simulations, revealing good agreement. The presented model could be easily integrated into commercial circuit simulators because of its accuracy and simplicity.

Keywords

Tunnel field-effect transistor (TFET) Gate-all-around (GAA) Dual-material GAA-TFET Band-to-band tunneling (BTBT) Evanescent mode 

References

  1. 1.
    Frank, D.J., Dennard, R.H., Nowak, E., Solomon, P.M., Taur, Y., Wong, H.S.P.: Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE 89(3), 259–288 (2001).  https://doi.org/10.1109/5.915374 CrossRefGoogle Scholar
  2. 2.
    Roy, K., Mukhopadhyay, S., Mahmoodi-Meimand, H.: Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc. IEEE 91(2), 305–327 (2003).  https://doi.org/10.1109/JPROC.2002.808156 CrossRefGoogle Scholar
  3. 3.
    Seabaugh, A.C., Zhang, Q.: Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE 98(12), 2095–2110 (2010).  https://doi.org/10.1109/JPROC.2010.2070470 CrossRefGoogle Scholar
  4. 4.
    Koswatta, S.O., Lundstrom, M.S., Nikonov, D.E.: Performance comparison between pin tunneling transistors and conventional MOSFETs. IEEE Trans. Electron Dev. 56(3), 456–465 (2009).  https://doi.org/10.1109/TED.2008.2011934 CrossRefGoogle Scholar
  5. 5.
    Toh, E.-H., Wang, G.H., Samudra, G., Yeo, Y.-C.: Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications. J. Appl. Phys. 103(10), 104504 (2008).  https://doi.org/10.1063/1.2924413 CrossRefGoogle Scholar
  6. 6.
    Kumar, M.J., Janardhanan, S.: Doping-less tunnel field effect transistor: design and investigation. IEEE Trans. Electron Dev. 60(10), 3285–3290 (2013).  https://doi.org/10.1109/TED.2013.2276888 CrossRefGoogle Scholar
  7. 7.
    Vishnoi, R., Kumar, M.J.: Compact analytical model of dual material gate tunneling field-effect transistor using interband tunneling and channel transport. IEEE Trans. Electron Dev. 61(6), 1936–1942 (2014).  https://doi.org/10.1109/ted.2014.2315294 CrossRefGoogle Scholar
  8. 8.
    Gholizadeh, M., Hosseini, S.E.: A 2-D analytical model for double-gate tunnel FETs. IEEE Trans. Electron Dev. 61(5), 1494–1500 (2014).  https://doi.org/10.1109/TED.2014.2313037 CrossRefGoogle Scholar
  9. 9.
    Toh, E.-H., Wang, G.H., Chan, L., Samudra, G., Yeo, Y.-C.: Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunction. Appl. Phys. Lett. 91(24), 243505 (2007).  https://doi.org/10.1063/1.2823606 CrossRefGoogle Scholar
  10. 10.
    Ionescu, A.M., Boucart, K., Moselund, K.E., Pott, V., Tsamados, D.: Small slope micro/nano-electronic switches. In: 2007. CAS 2007. International Semiconductor Conference, vol. 2, pp. 397–402. IEEE.  https://doi.org/10.1109/smicnd.2007.4519743
  11. 11.
    Gopalakrishnan, K., Griffin, P.B., Plummer, J.D.: I-MOS: a novel semiconductor device with a subthreshold slope lower than kT/q. In: Electron Devices Meeting, 2002. IEDM’02. International, pp. 289–292. IEEE.  https://doi.org/10.1109/iedm.2002.1175835
  12. 12.
    Nathanson, H.C., Newell, W.E., Wickstrom, R.A., Davis, J.D.: The resonant gate transistor. IEEE Trans. Electron Dev. 14(3), 117–133 (1967).  https://doi.org/10.1109/T-ED.1967.15912 CrossRefGoogle Scholar
  13. 13.
    Yeo, K.H., Suk, S.D., Li, M., Yeoh, Y., Cho, K.H., Hong, K-H., Yun, S., et al.: Gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 15 nm length gate and 4 nm radius nanowires. In: Electron Devices Meeting, 2006. IEDM’06. International, pp. 1–4. IEEE.  https://doi.org/10.1109/iedm.2006.346838
  14. 14.
    Shao, Q., Zhao, C., Wu, C., Zhang, J., Zhang, L., Yu, Z.: Compact model and projection of silicon nanowire tunneling transistors (NW-tFETs). In: 2013 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC), pp. 1–2. IEEE.  https://doi.org/10.1109/edssc.2013.6628137
  15. 15.
    Verhulst, A.S., Sorée, B., Leonelli, D., Vandenberghe, W.G., Groeseneken, G.: Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor. J. Appl. Phys. 107(2), 024518 (2010).  https://doi.org/10.1063/1.3277044 CrossRefGoogle Scholar
  16. 16.
    Saurabh, S., Kumar, M.J.: Novel attributes of a dual material gate nanoscale tunnel field-effect transistor. IEEE Trans. Electron Dev. 58(2), 404–410 (2011).  https://doi.org/10.1109/ted.2010.2093142 CrossRefGoogle Scholar
  17. 17.
    Bardon, M.G., Neves, H.P., Puers, R., Van Hoof, C.: Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions. IEEE Trans. Electron Dev. 57(4), 827–834 (2010).  https://doi.org/10.1109/TED.2010.2040661 CrossRefGoogle Scholar
  18. 18.
    Vishnoi, R., Kumar, M.J.: A pseudo-2-D-analytical model of dual material gate all-around nanowire tunneling FET. IEEE Trans. Electron Dev. 61(7), 2264–2270 (2014).  https://doi.org/10.1109/ted.2014.2321977 CrossRefGoogle Scholar
  19. 19.
    Kumar, S., Raj, B.: Compact channel potential analytical modeling of DG-TFET based on evanescent-mode approach. J. Comput. Electron. 14(3), 820–827 (2015).  https://doi.org/10.1007/s10825-015-0718-9 CrossRefGoogle Scholar
  20. 20.
    Khaveh, H.R.T., Mohammadi, S.: Potential and drain current modeling of gate-all-around tunnel FETs considering the junctions depletion regions and the channel mobile charge carriers. IEEE Trans. Electron Dev. 63(12), 5021–5029 (2016).  https://doi.org/10.1109/TED.2016.2619761 CrossRefGoogle Scholar
  21. 21.
    Gupta, S.K.: Threshold voltage model of junctionless cylindrical surrounding gate MOSFETs including fringing field effects. Superlattices Microstruct. 88, 188–197 (2015).  https://doi.org/10.1016/j.spmi.2015.09.001 CrossRefGoogle Scholar
  22. 22.
    Aouaj, A., Bouziane, A., NouaÇry, A.: Analytical 2D modeling for potential distribution and threshold voltage of the short channel fully depleted cylindrical/surrounding gate MOSFET. Int. J. Electron. 92(8), 437–443 (2005)CrossRefGoogle Scholar
  23. 23.
    Lee, J., Shin, H.: Evanescent-mode analysis of short-channel effects in MOSFETs. J. Kor. Phys. Soc. 44(1), 50–55 (2004)CrossRefGoogle Scholar
  24. 24.
    Dash, S., Mishra, G.P.: A new analytical threshold voltage model of cylindrical gate tunnel FET (CG-TFET). Superlattices Microstruct. 86, 211–220 (2015)CrossRefGoogle Scholar
  25. 25.
    Silvaco ATLAS.: Device simulation software, Silvaco Int., Santa Clara, CA (2013)Google Scholar
  26. 26.
    Vandenberghe, W.G., Sorée, B., Magnus, W., Groeseneken, G., Fischetti, M.V.: Impact of field-induced quantum confinement in tunneling field-effect devices. Appl. Phys. Lett. 98(14), 143503 (2011)CrossRefGoogle Scholar
  27. 27.
    Marin, E.G., Ruiz, F.G., Schmidt, V., Godoy, A., Riel, H., Gámiz, F.: Analytic drain current model for III–V cylindrical nanowire transistors. J. Appl. Phys. 118(4), 044502 (2015)CrossRefGoogle Scholar
  28. 28.
    Omura, Y., Horiguchi, S., Tabe, M., Kishi, K.: Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFETs. IEEE Electron Dev. Lett. 14(12), 569–571 (1993)CrossRefGoogle Scholar
  29. 29.
    Sajjad, R.N., Chern, W., Hoyt, J.L., Antoniadis, D.A.: Trap assisted tunneling and its effect on subthreshold swing of tunnel FETs. IEEE Trans. Electron Dev. 63(11), 4380–4387 (2016)CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  • Varun Mishra
    • 1
  • Yogesh Kumar Verma
    • 1
  • Prateek Kishor Verma
    • 1
  • Santosh Kumar Gupta
    • 1
  1. 1.Motilal Nehru National Institute of Technology AllahabadAllahabadIndia

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