Quaternary Quantum/Reversible Half-Adder, Full-Adder, Parallel Adder and Parallel Adder/Subtractor Circuits

  • Asma Taheri Monfared
  • Majid HaghparastEmail author
  • Kamalika Datta


Multiple valued quantum logic is a promising research area in quantum computing technology having several advantages over binary quantum logic. Adder circuits as well as subtractor circuits are the major components of various computational units in computers and other complex computational systems. In this paper, we propose a quaternary quantum reversible half-adder circuit using quaternary 1-qudit gates, 2-qudit Feynman and Muthukrishnan-Stroud gates. Then we propose a quaternary quantum reversible full adder and a quaternary quantum parallel adder circuit. In addition, we propose a quaternary quantum reversible parallel adder/subtractor circuit. The proposed designs are compared with existing designs and improvements in terms of hardware complexity, quantum cost, number of constant inputs and garbage outputs are reported.


Multiple valued logic Reversible logic Quantum computing Quaternary logic Quantum reversible adder circuits 



  1. 1.
    Landaurer, R.: Irreversibility and heat generation in the computational process. IBM J. Res. Dev. 5, 183–191 (1961)CrossRefGoogle Scholar
  2. 2.
    Bennett, C. H.: Logical reversibility of computation. IBM J. Res. Dev. 17(6), 525–532 (1973)Google Scholar
  3. 3.
    Perkowski, M., Al-Rabadi, A., Kerntopf, P., Buller, A., Chrzanowska-Jeske, M., Mishchenko, A., Azad Khan, M., Coppola, A., Yanushkevich, S., Shmerko, V., Jozwiak, L.: A general decomposition for reversible logic. In: Proceedings of RM. 119–138 (2001)Google Scholar
  4. 4.
    Perkowski, M., Kerntopf, P.: Reversible logic. Invited tutorial. In: Proceedings of EURO MICRO (2001)Google Scholar
  5. 5.
    Babu, H. M. H., Chowdhury, A. R.: Design of a reversible binary coded decimal adder by using reversible 4-bit parallel adder. In 18th International Conference on VLSI Design Held Jointly with 4th International Conference on Embedded Systems Design, pp. 255–260. IEEE (2005)Google Scholar
  6. 6.
    Nielson, M. A., Chuang, I. L.: Quantum Computation and Quantum Information, Cambridge Series on Information and the Natural Sciences (Cambridge University Press) (2000)Google Scholar
  7. 7.
    Satsangi, S., Patvardhan, C.: Enhanced quantum inspired evolutionary algorithm for automatic synthesis of reversible circuits. Int. J. Eng. Technol. Sci. Res. 3(1), 34–45 (2016)Google Scholar
  8. 8.
    Moghadam, M.Z., Navi, K., Kalemati, M.: A novel reversible design for double edge triggered flip-flops and new designs of reversible sequential circuits. Comput. Syst. Sci. Eng. 29(3), 197–204 (2014)Google Scholar
  9. 9.
    Bechmann-Pasquinucci, H., Peres, A.: Quantum cryptography with 3-state systems. Phys. Rev. Lett. 85(15), 3313–3316 (2000)ADSMathSciNetCrossRefzbMATHGoogle Scholar
  10. 10.
    Bourennane, M., Karlsson, A., Björk, G.: Quantum key distribution using multilevel encoding. Phys. Rev. A. 64(1), 012306 (2001)ADSCrossRefGoogle Scholar
  11. 11.
    Greentree, A.D., Schirmer, S.G., Green, F., Hollenberg, L.C., Hamilton, A.R., Clark, R.G.: Maximizing the Hilbert space for a finite number of distinguishable quantum states. Phys. Rev. Lett. 92(9), 097901 (2004)ADSCrossRefGoogle Scholar
  12. 12.
    Miller, D.M., Thornton, M.A.: Multiple valued logic: concepts and representations. Synth. Lect. Digit. Circ. Syst. 2(1), 1–127 (2007)Google Scholar
  13. 13.
    Curtis, E., Perkowski, M.: A transformation based algorithm for ternary reversible logic synthesis using universally controlled ternary gates. Proc. IWLS. 2004, 345–352 (2004)Google Scholar
  14. 14.
    Zadeh, R.P., Haghparast, M.: A new reversible/quantum ternary comparator. Aust. J. Basic Appl. Sci. 5(12), 2348–2355 (2011)Google Scholar
  15. 15.
    Khan, M.H., Perkowski, M.A., Khan, M.R., Kerntopf, P.: Ternary GFSOP minimization using kronecker decision diagrams and their synthesis with quantum cascades. J. Mult. Valued Logic Soft Comput. 11(5/6), 567 (2005)zbMATHGoogle Scholar
  16. 16.
    Khan, M. H., Perkowski, M. A., Khan, M. R.: Ternary Galois field expansions for reversible logic and Kronecker decision diagrams for ternary GFSOP minimization [Galois field sum of products]. In Proceeding: 34th International Symposium on Multiple-Valued Logic, 2004., pp. 58–67. IEEE (2004)Google Scholar
  17. 17.
    Khan, M. H., Perkowski, M.: Quantum realization of ternary encoder and decoder. In: Proceedings of the 7th International Symposium Representations and Methodology of Future Computing Technologies (RM2005), Tokyo, Japan (2005)Google Scholar
  18. 18.
    Khan, M.H.: Design of reversible/quantum ternary multiplexer and demultiplexer. Eng. Lett. 13(2), 65–69 (2006)Google Scholar
  19. 19.
    Monfared, A.T., Haghparast, M.: Design of new quantum/reversible ternary subtractor circuits. J. Circuit, Syst. Comp. 25(02), 1650014 (2016)CrossRefGoogle Scholar
  20. 20.
    Monfared, A.T., Haghparast, M.: Novel design of quantum/reversible ternary comparator circuits. J. Comput. Theor. Nanosci. 12(12), 5670–5673 (2015)CrossRefGoogle Scholar
  21. 21.
    Houshmand, P., Haghparast, M.: Design of a novel quantum reversible ternary up-counter. Int. J. Quantum Inf. 13(05), 1550038 (2015)CrossRefzbMATHGoogle Scholar
  22. 22.
    Haghparast, M., Wille, R., Monfared, A.T.: Towards quantum reversible ternary coded decimal adder. Quantum Inf. Process. 16(11), 284 (2017)MathSciNetCrossRefzbMATHGoogle Scholar
  23. 23.
    Monfared, A.T., Haghparast, M.: Designing new ternary reversible subtractor circuits. Microprocess. Microsyst. 53, 51–56 (2017)CrossRefGoogle Scholar
  24. 24.
    Khan, M. H., Perkowski, M. A.: GF (4) based synthesis of quaternary reversible/quantum logic circuits. In 37th International Symposium on Multiple-Valued Logic (ISMVL'07), pp. 11–11. IEEE (2007)Google Scholar
  25. 25.
    Khan, M. H.: Reversible realization of quaternary decoder, multiplexer, and demultiplexer circuits. In 38th International Symposium on Multiple Valued Logic (Ismvl 2008), pp. 208–213. IEEE (2008)Google Scholar
  26. 26.
    Jahangir, I., Das, A.: On the design of quaternary comparators. In: 2010 13th International Conference on Computer and Information Technology (ICCIT), pp. 241–246. IEEE (2010)Google Scholar
  27. 27.
    Khan, M.H.: Synthesis of quaternary reversible/quantum comparators. J. Syst. Archit. 54(10), 977–982 (2008)CrossRefGoogle Scholar
  28. 28.
    Khan, M. M. M., Biswas, A. K., Chowdhury, S., Tanzid, M., Mohsin, K. M., Hasan, M., Khan, A. I.: Quantum realization of some quaternary circuits. In: TENCON 2008-2008 IEEE Region 10 Conference. 19–21 (2008)Google Scholar
  29. 29.
    Khan, M. H.: Scalable architectures for Design of Reversible Quaternary Multiplexer and Demultiplexer Circuits. In: 2009 39th International Symposium on Multiple-Valued Logic. 343–348. IEEE (2009)Google Scholar
  30. 30.
    Khan, M. H., Thapliyal, H.: Reversible logic based mapping of quaternary sequential circuits using QGFSOP expression. In: 2015 IEEE Computer Society Annual Symposium on VLSI. 297–302 (2015)Google Scholar
  31. 31.
    Meena, J. K., Jain, S. C., Gupta, H., Gupta, S.: Synthesis of balanced quaternary reversible logic circuit. In: 2015 International Conference on, Circuit, Power and Computing Technologies (ICCPCT). 1–6. IEEE (2015)Google Scholar
  32. 32.
    Haghparast, M., Monfared, A. T.: Designing novel quaternary quantum reversible subtractor circuits. Int. J. Theor. Phys. 57(1), 1–12 (2017)Google Scholar
  33. 33.
    Haghparast, M., Dousttalab, N.: Design of new reversible quaternary flip-flops. Int. J. Quantum Inf. 15(04), 1750024 (2017)MathSciNetCrossRefzbMATHGoogle Scholar
  34. 34.
    Haghparast, M., Monfared, A.T.: Novel quaternary quantum decoder, multiplexer and Demultiplexer circuits. Int. J. Theor. Phys. 56(5), 1694–1707 (2017)CrossRefzbMATHGoogle Scholar
  35. 35.
    Muthukrishnan, A., Stroud Jr., C.R.: Multivalued logic gates for quantum computation. Phys. Rev. A. 62(5), 052309 (2000)ADSMathSciNetCrossRefGoogle Scholar
  36. 36.
    Thapliyal, H.: Mapping of subtractor and adder-subtractor circuits on reversible quantum gates. Transaction on Computer Science XXVII. LNCS, vol. 9570, pp. 10–34. Springer, Heidelberg (2016)Google Scholar
  37. 37.
    Taheri Monfared, A., Haghparast, M.: Design of novel quantum/reversible ternary adder circuits. Int. J. Electron Lett. 5(2),1–9 (2016)Google Scholar
  38. 38.
    Haghparast, M., Bolhassani, A.: Optimized parity preserving quantum reversible full adder/subtractor. Int. J. Quantum Inf. 14, 1650019 (2016)CrossRefzbMATHGoogle Scholar
  39. 39.
    Bose, A., Babu, H. M. H.: Optimized designs of reversible fault tolerant BCD adder and fault tolerant reversible carry skip BCD adder. In 2015 18th International Conference on Computer and Information Technology (ICCIT), pp. 202–207. IEEE (2015)Google Scholar
  40. 40.
    Khan, M.H.: A recursive method for synthesizing quantum/reversible quaternary parallel adder/subtractor with look-ahead carry. J. Syst. Archit. 54(12), 1113–1121 (2008)CrossRefGoogle Scholar
  41. 41.
    Mandal, S. B., Chakrabarti, A., Sur-Kolay, S.: A synthesis method for quaternary quantum logic circuits. In Progress in VLSI Design and Test, pp. 270–280. Springer, Berlin (2012)Google Scholar
  42. 42.
    Thapliyal, H., Ranganathan, N.: A new reversible design of bcd adder. In Design, Automation & Test in Europe, pp. 1–4. IEEE (2011)Google Scholar
  43. 43.
    Burignat, S., De Vos, A.: Test of a majority-based reversible (quantum) 4 bits ripple-carry adder in adiabatic calculation. In Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference, pp. 368–373. IEEE (2011)Google Scholar
  44. 44.
    Mohammadi, M., Eshghi, M., Haghparast, M., Bahrololoom, A.: Design and optimization of reversible bcd adder/subtractor circuit for quantum and nanotechnology based systems. World Appl. Sci. J. 4(6), 787–792 (2008)Google Scholar
  45. 45.
    Islam, M.: A novel quantum cost efficient reversible full adder gate in nanotechnology. arXiv:1008.3533 (2010)Google Scholar
  46. 46.
    Chattopadhyay, T., Taraphdar, C., Roy, J.N.: Quaternary Galois field adder based all-optical multivalued logic circuits. Appl. Opt. 48(22), E35–E44 (2009)ADSCrossRefGoogle Scholar
  47. 47.
    Khan, M. H.: Quantum realization of quaternary Feynman and Toffoli gates. In 2006 International Conference on Electrical and Computer Engineering, pp. 157–160. IEEE (2006)Google Scholar

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Authors and Affiliations

  1. 1.Department of Computer, Abadan BranchIslamic Azad UniversityAbadanIran
  2. 2.Department of Computer Engineering, Yadegar -e- Imam Khomeini (RAH) Shahre Rey BranchIslamic Azad UniversityTehranIran
  3. 3.School of Computer Science and EngineeringNanyang Technological University SingaporeSingaporeSingapore

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