Cluster Computing

, Volume 22, Supplement 3, pp 7063–7068 | Cite as

High performance Viterbi decoder design

  • V. KavithaEmail author
  • S. Mohanraj


Viterbi decoder may be a regular module over correspondence framework in which energy also deciphering inactivity need aid demand. Register Exchange (RE) building design need the most reduced deciphering inactivity l. However, it is not suitable for correspondence framework due to its secondary force utilization. In this paper, it is recommended another SMU structural engineering which combines the idea of the trace-forward and also trace-back. Those deciphering inactivity of the suggested SMU calculation may be main L+M. Besides, we display a force productive building design for the recommended SMU algorithm. The recommended structural engineering is executed in Xilinx ISE 12. 3 for focus gadget may be Vertex6 FPGA. The control utilization of the suggested construction modeling is marginally higher over those 3-pointer.


Viterbi decoder SMU algorithm Register exchange architecture 


  1. 1.
    Viterbi, A.J.: Convolutional codes and their performance in communication systems. IEEE Trans. Commun. 1910, 751–772 (1971)MathSciNetCrossRefGoogle Scholar
  2. 2.
    Chu, C.Y., Haung, Y.C., Wu, A.Y.: Power efficient low latency survivor memory architecture for Viterbi decoder. Commun. IEEE Trans. (2008). CrossRefGoogle Scholar
  3. 3.
    Feygin, G., Gulak, P.G.: Architectural tradeoffs for survivor sequence memory management in Viterbi decoders. IEEE Trans. Commun. 41(3), 425–429 (1993)CrossRefGoogle Scholar
  4. 4.
    Blck, P.J., Meng, T.H.: A 140-mb/s 32-state, radix-4 Viterbi decoder. IEEE J. Solid-State Circuits 27(6), 1877–1885 (1992)CrossRefGoogle Scholar
  5. 5.
    Gang, Y., Erdogan, A.T., Arslan, T.: An efficient pre-traceback architecture for the Viterbi decoder targeting wireless communication applications. IEEE Trans. Circuits Syst. I 52(6), 1148–1156 (2005)MathSciNetCrossRefGoogle Scholar
  6. 6.
    Wicker, S.B.: Error Control Systems for Digital Communication and Storage. Prentice Hall, Englewood Cliffs (1995)zbMATHGoogle Scholar
  7. 7.
    Chan, M.-H., Lee, W.-T., Lin, M.-C., Chen, L.-G.: IC design of an adaptive viterbi decoder. IEEE Trans. on Consumer Electron. 42, 52–61 (1996)CrossRefGoogle Scholar
  8. 8.
    Seki, K., Kubota, S., Mizoguchi, M., Kato, S.: Very low power consumption viterbi decoder lsic employing the SST (scarce state transition) scheme for multimedia mobile communications. Electronics-Letters, IEE 30(8), 637–639 (1994)CrossRefGoogle Scholar
  9. 9.
    Lang, L., Tsui, C.Y., Cheng, R.S.: Low power soft output viterbi decoder scheme for turbo code decoding. Proc. Int. Symp. on Circuits Syst. 2, 369–1372 (1997)Google Scholar
  10. 10.
    Kang, I., Willson Jr., A.N.: Low-power Viterbi decoder for CDMA mobile terminals. IEEE J. of Solid-State Circuits 33(3), 473–482 (1998)CrossRefGoogle Scholar

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© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringM.Kumarasamy College of EngineeringKarurIndia

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