A high energy-efficient and area-saving two-step switching method for the dual-capacitive arrays (DCAs) successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed. By adopting two-step architecture, spilt-capacitor method, monotonic switching scheme, four-input comparator and C–2C capacitor array, the proposed procedure achieves 99.84% saving in average switching energy and 84.38% reduction in total capacitance compared to the conventional scheme when applied to a 10-bit SAR ADC, meanwhile achieving DNL and INL only 0.234LSB and 0.281LSB, respectively. Furthermore, this method eliminates reset energy, while achieves a compromise among energy, area, and linearity.
SAR ADC Four-input comparator Switching scheme Energy efficiency Two-step
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This work is supported by the innovation wisdom base for wide bandgap semiconductor and micro-nano electronics of China (B12026), the National Natural Science Foundation of China (61076031), Aeronautical Science Foundation of China (20120281), the Natural Science Foundation of Shaanxi Province, China (2019JQ553, 2016JM6067), Strategic international scientific and technological innovation cooperation key projects (2016YFE0207000).
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