A wide-range all-digital phase inversion DLL for high-speed DRAMs
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This paper presents two new all-digital phase inversion delay-locked loop (PIDLL) architectures for high-speed DRAMs. The proposed PIDLLs utilize a new phase inversion scheme to reduce the total number of delay elements in the digitally controlled delay line by approximately one-half, enabling shorter locking time, lower power consumption, reduced jitter performance, and a smaller area, while maintaining a wide operating frequency range. A new area-efficient digital feedback delay element is proposed to achieve high delay resolution and linear delay characteristics. To verify the proposed PIDLL architecture, two PIDLL chips were fabricated and measured. The first PIDLL is fabricated in a 0.13-µm 1.2-V CMOS process and operates over a frequency range of 0.1–1.5 GHz. Using a variable SAR-based hybrid search algorithm, the first chip achieves fast locking time of less than 38 clock cycles and dissipates the power of 5.9 mW from at 1 GHz and exhibits a measured peak-to-peak (p–p) output clock jitter of 11.25 ps at 1.5 GHz. The second PIDLL is fabricated in a 65-nm 1.0-V CMOS process, occupies an area of only 0.015 mm2, and operates over a frequency range of 1.5–5.0 GHz. The second PIDLL achieves a p–p output clock jitter of 12.3 ps and dissipates the power of 6.6 mW at 5 GHz.
KeywordsDRAM Delay-locked loop DLL Memory DDR4 DDR5
This research was funded and conducted under “the Competency Development Program for Industry Specialists” of the Korean Ministry of Trade, Industry and Energy (MOTIE), operated by Korea Institute for Advancement of Technology (KIAT). (No. N0001883, HRD program for N0001883). This work was also supported by National Research Foundation of Korea (NRF 2019R1A2C-1010017). The EDA tools were supported by IDEC.
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