Analog Integrated Circuits and Signal Processing

, Volume 101, Issue 2, pp 307–317 | Cite as

Low-power high-speed CMOS double tail dynamic comparator using self-biased amplification stage and novel latch stage

  • Avaneesh K. DubeyEmail author
  • R. K. Nagaria


This paper presents a low voltage double-tail dynamic comparator (DTDC) for fast and power-efficient data conversion. The amplification stage of the proposed DTDC is designed using self-biasing technique, which helps to reduce external biasing requirement to bias bulk/gate of the transistors. The self-biasing technique controls threshold voltage (Vth) of the transistors either for fast switching (low-Vth) or for low power dissipation (high-Vth). The latch stage of the proposed DTDC is designed with novel dynamic CMOS inverters to improve the regeneration speed. The mathematical equations for delay and offset voltage are derived for the proposed DTDC and improvements are mentioned. The proposed DTDC is designed in CADENCE and simulated with SPECTRE using 45 nm CMOS process technology at the low power supply of 0.8 V to verify the outcomes. The simulation results reveal that the delay and power dissipation of the proposed DTDC are 166.29 pS and 2.3 µW respectively. The analysis of 1-sigma offset error is performed using Monte-Carlo simulation. Here, the mismatch and process variation are considered and the samples are generated randomly till 200 samples (runs). Additionally, the peak input voltage error due to kickback noise is 0.219 mV for a differential input voltage of 5 mV.


Double tail dynamic comparator Offset voltage Low-power Kickback noise CMOS 



The authors are indebted to Ministry of Electronics and Information Technology (MeitY), Govt. of India, New Delhi, for providing research funds. The authors would also thank the PARAM Lab and VLSI Lab of MN National Institute of Technology Allahabad for providing us the research environment and computational infrastructure.


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© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringM.N. National Institute of Technology AllahabadAllahabadIndia

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