Analog Integrated Circuits and Signal Processing

, Volume 101, Issue 3, pp 431–440 | Cite as

An efficient and unified 2D-inverse integer cosine transform (IICT) FPGA-hardware implementation for HEVC standard

  • Ahmed KammounEmail author
  • Fatma Belghith
  • Hassen Loukil
  • Nouri Masmoudi


The HEVC video coding standard supports different transform sizes ranging from 4-point to 32-point. In fact, multiple transform sizes improve coding efficiency, but increase as well the computational complexity. Hardware decoders apply different techniques to satisfy real-time requirements. This paper describes a novel design methodology of a unified 2D inverse core transform IICT. The hardware architecture is based on a 1D-IICT block and a transpose buffer FIFO memory used to store the intermediate values of 1D transform. All this process is controlled in such a way to reduce the hardware and memory resources. To support the different transform sizes, matrix multiplications are simplified based on transform blocks decomposition into fixed-size sub-blocks in previous works. The architecture was developed for an FPGA device. Synthesis results on Startix III FPGA device show that the proposed design, operating at 266 MHz, is sufficient to decode high resolution videos using only 10% of total pins and about 33% of the hardware resources offered.


High efficiency video coding (HEVC) 2D-inverse core transform FIFO 



  1. 1.
    ITU-T Recommendation H.265 and ISO/IEC 23008–2 MPEG-H Part 2, High Efficiency Video Coding (HEVC) (2013).Google Scholar
  2. 2.
    Gary, J. S., Woo-Jin, H., & Thomas, W. (2012). Overview of the high efficiency video coding (HEVC) standard. In Circuits and systems for video technology.Google Scholar
  3. 3.
    Wiegand, T., Sullivan, G. J., Bjøntegaard, G., & Luthra, A. (2003). Overview of the H.264/AVC Video Coding Standard. IEEE Transactions on Circuits And Systems for Video Technology, 13(7), 560–576.CrossRefGoogle Scholar
  4. 4.
    Seo, Chanwon, & Han, Jongki. (2010). Video coding performance for ierarchical coding block and transform block structures. Korea Society Broading Engineers Magazine, 15(4), 23–34.Google Scholar
  5. 5.
    Kim, I.-K., Min, J., Lee, T., Han, W.-J., & Park, J. H. (2012). Block partitioning structure in the HEVC standard. IEEE Transactions on Circuits and Systems for Video Technology, 22(12), 1697–1706.CrossRefGoogle Scholar
  6. 6.
    Bossen, F., Bross, B., Suhring, K., & Flynn, D. (2012). HEVC complexity and implementation analysis. IEEE Transactions on Circuits and Systems for Video Technology, 22(12), 1685–1696.CrossRefGoogle Scholar
  7. 7.
    Patel, D., Lad, T., & Shah, D. (2015). Review on intra-prediction in high efficiency video coding (HEVC) standard. International Journal of Computer Applications, 975, 8887.Google Scholar
  8. 8.
    Chih-Ming, F., Alshina, E., Alshin, A., Huang, Y.-W., Chen, C.-Y., & Tsai, C.-Y. (2012). Sample adaptive offset in the HEVC standard. IEEE Transactions on Circuits and Systems for Video Technology, 22(12), 1755–1764.CrossRefGoogle Scholar
  9. 9.
    Ohm, J.-R., Sullivan, G., Schwarz, H., Tan, T. K., & Wiegand, T. (2012). Comparison of the coding efficiency of video coding standards including high efficiency video coding (HEVC). IEEE Transactions on Circuits and Systems for Video Technology, 22(12), 1669–1684.CrossRefGoogle Scholar
  10. 10.
    Budagavi, M., Fuldseth, A., Bjøntegaard, G., Sze, V., & Sadafale, M. (2013). Core transform design in the high efficiency video coding (HEVC) standard. IEEE Journal Of Selected Topics In Signal Processing, 7(6), 1029–1041.CrossRefGoogle Scholar
  11. 11.
    Kammoun, A., Belghith, F., Loukil, H., & Masmoudi, N. (2016). An optimized and unified architecture design for H.265/HEVC 1-D inverse core transform IEEE IPAS’16. In International Image Processing Applications and Systems Conference.Google Scholar
  12. 12.
    Chang, C.-W., Hsu, H.-F., Fan, C.-P., Chung-Bin, W., & Robert, C.-H. C. (2016). A fast algorithm-based cost-effective and hardware-efficient unified architecture design of 4x4, 8x8, 16x16, and 32x32 inverse core transforms for HEVC. Journal of Signal Processing Systems, 82, 69–89.CrossRefGoogle Scholar
  13. 13.
    Shen, S., Shen, W., Fan, Y., & Zeng, X. (2012). A unified 4/8/16/32-point integer IDCT architecture for multiple video coding standards. IEEE International Conference on Multimedia and Expo (ICME) (pp. 788–793).Google Scholar
  14. 14.
    Ahmed, A., & Shahid, M. U. (2012). N point DCT VLSI architecture for emerging HEVC standard. VLSI Design, 2012, 1–13.MathSciNetCrossRefGoogle Scholar
  15. 15.
    Kammoun, M., Maamouri, E., Atitallah, A. B., & Masmoudi, N. (2016). An optimized hardware architecture Of 4x4, 8x8, 16x16 and 32x32 inverse transform for HEVC. In ATSIP: international conference on advanced technologies for signal and image processing.Google Scholar
  16. 16.
    Kalali, E., & Hamzaoglu, I. (2015). FPGA implementations of HEVC inverse DCT using high-level synthesis. In IEEE design and architectures for signal and image processing (DASIP), Poland.Google Scholar
  17. 17.
    Sun, H., Zhou, D., & Goto, S. (2014). A low-cost VLSI architecture of multiple-size IDCT for H265/HEVC. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 97(12), 2467–2476.CrossRefGoogle Scholar
  18. 18.
  19. 19.

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© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.National School of Engineering SfaxUniversity of SfaxSfaxTunisia

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