NanoCMOS optimized DVCC-based quadrature voltage controlled oscillator performances prediction through bisquare-weights method

  • Houda DaoudEmail author
  • Samir Bensalem
  • Sawssan Lahiani
  • Chayma Bensalem
  • Mourad Loulou


This paper dealt with the prediction of optimized quadrature voltage controlled oscillator (QVCO) performances for the upcoming CMOS nanoprocess using the robust bisquare weights (BW) method. Using differential voltage current conveyor, the QVCO was optimized for low power consumption with TSMC 0.18 µm CMOS process under ± 0.9 V supply voltage and relying on the Heuristic method. To provide solutions to the nanoscale CMOS challenges, a synoptic of nanoCMOS circuit performances prediction including the BW method was proposed to predict the performances of the optimized QVCO circuit. Some predicted performances for 45–22 nm process nodes were obtained in order to solve design challenges generated by upcoming analog high frequency (HF) systems with severe requirements. The behaviour of the optimized QVCO performances with process scaling were detailed.


QVCO optimization Low power consumption Bisquare weights method Predicted QVCO performances Process scaling New HF systems 



  1. 1.
    Spiridon, S. (2016). Toward 5G software defined radio receiver front-ends. Berlin: Springer.CrossRefGoogle Scholar
  2. 2.
    Nath, V. (2017). In Proceedings of the International Conference on Nano-electronics, Circuits & Communication Systems. Springer.Google Scholar
  3. 3.
    Senani, R., Bhaskar, D. R., Singh, V. K., & Sharma, R. K. (2016). Sinusoidal oscillators and waveform generators using modern electronic circuit building blocks. Berlin: Springer.CrossRefGoogle Scholar
  4. 4.
    Jin, J. (2017). Novel quadrature voltage-controlled oscillator using capacitor coupling. Institute of Electrical Telecom Engineering, 0, 1–7.Google Scholar
  5. 5.
    Bajestan, M. M., Rezaei, V. D., & Entesari, K. (2015). A low phase-noise wide tuning-range quadrature oscillator using a transformer-based dual-resonance ring. Transaction MICR The Techn, 63, 1142–1153.CrossRefGoogle Scholar
  6. 6.
    Yesil, A., Kacar, F., & Gurkan, K. (2016). Design and experimental evaluation of quadrature oscillator employing single fb–vdba. Journal of Electrical Engineering, 67, 137–142.CrossRefGoogle Scholar
  7. 7.
    Arora, S. T., & Gupta, S. (2018). A new voltage mode quadrature oscillator using grounded capacitors: An application of CDBA. International Journal of Engineering, Science and Technology, Science Direct, 21, 1–7.Google Scholar
  8. 8.
    Summart, S., Thongsopa, C., & Jaikla, W. (2015). New current-controlled current-mode sinusoidal quadrature oscillators using cdtas. International Journal of Electronics and Communications, 69, 62–68.CrossRefGoogle Scholar
  9. 9.
    Prasad, D., Ahmad. J. & Srivastava, M. (2017). New cm/vm 3rd-order quadrature oscillator using vdccs. In Applied System Innovation Conference.Google Scholar
  10. 10.
    Chien, C. H. (2013). Voltage- and current-modes sinusoidal oscillator using a single differential voltage current conveyor. Journal of Applied Sciences and Engineering, 16, 395–404.Google Scholar
  11. 11.
    Chien, H. C., & Chen, C. Y. (2014). CMOS realization of single-resistance-controlled and variable frequency dual-mode sinusoidal oscillators employing a single DVCCTA with all-grounded passive components. Microelectronics Journal, 45, 226–238.CrossRefGoogle Scholar
  12. 12.
    Minaei, S., & Yuce, E. (2010). Novel voltage-mode all-pass filter based on using dvccs. Circuits, Systems and Signal Processing, 29, 391–402.CrossRefzbMATHGoogle Scholar
  13. 13.
    Kwawsibsam, A., Sreewirote, B. & Jaikla, W. (2011). Third-order voltage-mode quadratrue oscillator using ddcc and otas. In Circuit System and Simulation Conference, pp 317–321.Google Scholar
  14. 14.
    Khan, I., Beg, P., & Ahmed, T. M. (2017). First order current mode filters and multiphase sinusoidal oscillators using cmos mocciis. Arabian Journal for Science and Engineering, 32, 146–149.Google Scholar
  15. 15.
    Chaturvedi, B., & Maheshwari, S. (2013). Third-order quadrature oscillator circuit with current and voltage outputs. ISRN Electronics, 2013.
  16. 16.
    Abdalla, K. K., Bhaskar, D. R., & Senani, R. (2012). Configuration for realizing a current-mode universal filter and dual-mode quadrature single resistor controlled oscillator. IET Circuits, Devices & Systems, 6, 159–167.CrossRefGoogle Scholar
  17. 17.
    Phatsornsiri, P., Lamun, P., Kumngern, M. & Torteanchai, U. (2014) Current-mode third-order quadrature oscillator using vdtas and grounded capacitors. In Information and Communications Technology, Electronic and Electrical Engineering Conference.Google Scholar
  18. 18.
    Pandey, N., & Pandey, R. (2015). Approach for third order quadrature oscillator realization. IET Circuits, Devices & Systems, 9, 161–171.CrossRefGoogle Scholar
  19. 19.
    Moore, G. (2003). No exponential is forever: But ‘forever’ can be delayed!. In Proceedings of IEEE International Conference S. S. C, 1. pp. 20–23.Google Scholar
  20. 20.
    Cao, Y. (2011). Predictive technology model for robust nanoelectronic design. Berlin: Springer.CrossRefGoogle Scholar
  21. 21.
    Björck, A. (1996). Numerical methods for least squares problems. SIAM: Philadelphia.CrossRefzbMATHGoogle Scholar
  22. 22.
    Daoud, Ben Salem, S. & Loulou, M. (2011). NanoCMOS folded cascode OTA performances prediction through least-square method. In Newcas Conference. pp. 337–340.Google Scholar
  23. 23.
    Daoud, H., Ben Salem, S., Zouari, S., & Loulou, M. (2013). Use of robust predictive method for nano-CMOS process Application to basic block analog circuit design. Journal of Circuits, Systems and Computers, 21, 1250061.CrossRefGoogle Scholar
  24. 24.
    Ben Salem, S., Ben Saied, A., & Masmoudi, D. S. (2016). High-performance current-controlled quadrature oscillator using an optimized ccii. Informacije MIDEM, 46, 91–99. Google Scholar
  25. 25.
    Dixit, V. K., Gupta, R. & Pal, K. (2014) Novel dvccs based voltage-mode first-order all pass sections. In International Conference on Signal Processing and Integrated Networks (SPIN), pp. 497–501.Google Scholar
  26. 26.
    Anuj, U., & Kirat, P. (2017). First order all pass, low pass and high pass filters using differential voltage current conveyors. Journal of Active & Passive Electronic Devices, 12, 275–284.Google Scholar
  27. 27.
    Mathur, K., Venkateswaran, P., & Nandi, R. (2017). All-pass filter based linear voltage controlled quadrature oscillator. Journal of Active and Passive Electronic Components Hindawi, 2017, 1–8. Scholar
  28. 28.
    Thitimahatthanagusol, P., Saetiaw, C., Thosdeekoraphat, T., Thongsopa, C., & Summart, S. (2017). CCCIIs-based first-order all-pass filter and quadrature oscillators. Journal of Circuits, Systems and Computers, 26, 1750094.CrossRefGoogle Scholar
  29. 29.
    Elwan, H.O. & Soliman, A.M. (1997) Novel cmos differential voltage current conveyor and its applications. In Proceedings of IEEE Circuits Devices System, 144.Google Scholar
  30. 30.
    Fakhfakh, M., Loulou, M., & Masmoudi, N. (2009). A novel heuristic for multi-objective optimization of analog circuit performances. Ana. Integ. Circ. Sign. Proc., 61, 47–64.CrossRefGoogle Scholar
  31. 31.
    Daoud, H., Laouej, D., Ben Salem, S. & Loulou, M. (2016) Design of discret time feed-forward cascaded ∆∑ modulator for wireless communication systems. In International Design & Test Symposium Conference, pp. 216–220.Google Scholar
  32. 32.
    Ibrahim, F., Usman, J., Ahmad, M.Y., Hamzah, N. & Teh, S.J. (2017) 2nd International Conference for Innovation in Biomedical Engineering and Life Sciences, Springer.Google Scholar
  33. 33.
    Huanga, G., Chena, Y., Zhoua, Y., Liua, P., & Liu, S. (2017). A new data processing algorithm based on model fitting for wireless sensor networks. Berlin: Springer.Google Scholar
  34. 34.
    Padgett, L. (2016). Practical statistical methods: a sas programming approach. Boca Raton: CRC Press, Taylor and Francis Group.Google Scholar
  35. 35.
    Balakrishnan, N., Chimitova, E., Galanova, N., & Vedernikova, M. (2013). Testing goodness of fit of parametric aft and ph models with residuals. Journals of Communications in Statistics-Simulation and Computation, 42, 1352–1367.CrossRefzbMATHGoogle Scholar
  36. 36.
    Bai, G P., Auth C., & et al. (2004). A 65 nm logic technology featuring 35 nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm2 SRAM cell. In IEEE International Electron Devices Meeting Conference, pp. 657–660.Google Scholar
  37. 37.
    Wu, C. C., Leung Y. K., & et al. (2002). A 90-nm CMOS device technology with high-speed, general-purpose, and low-leakage transistors for system on chip applications. In IEEE International Electron Devices Meeting Conference, pp. 65–68.Google Scholar
  38. 38.
    Thompson, S., Alavi M., & et al. (2001). An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7–1.4 V. In IEEE International Electron Devices Meeting Conference, pp. 257–260.Google Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  • Houda Daoud
    • 1
    • 2
    Email author
  • Samir Bensalem
    • 1
    • 2
  • Sawssan Lahiani
    • 2
  • Chayma Bensalem
    • 1
  • Mourad Loulou
    • 2
  1. 1.National Electronic and Telecommunication School of Sfax, Department of ElectronicsUniversity of SfaxSfaxTunisia
  2. 2.Electronic and Communications Group, LETI-laboratory, National School of Engineers of SfaxSfax UniversitySfaxTunisia

Personalised recommendations