A 171 GHz harmonic-mode PLL with − 14.2 dBm output power in 65 nm CMOS

  • Sanjeev Jain
  • Leonid BelostotskiEmail author
Mixed Signal Letter


This letter presents a harmonic-mode PLL (H-PLL) that avoids additional multiplication, filtering, and amplification stages and thus results in an area-efficient implementation. A proof-of-concept 57.5-mW 65-nm CMOS PLL prototype operating at 171 GHz provides − 14.2 dBm output power and a spur level of − 67.5 dBc. The PLL is built with a varactor-free 2fO VCO, which is tuned by varying transistor intrinsic capacitances via MOS bulk voltages.


Phase-locked loops mm-Wave PLL mm-Wave VCO 



The authors acknowledge support from Eyes High Postdoctoral Fellowship, University of Calgary, NSERC Discovery and Engage programs, Canada Research Chair program, and CMC Microsystems for subsidizing the chip fabrication. Special thanks go to Steven Durant from Virginia Diodes Inc. for support with measurements.


  1. 1.
    Tsai, K.-H., & Liu, S.-L. (2009). A 43. mW 96 GHz PLL in 65 nm CMOS. In ISSCC (pp. 276–277).Google Scholar
  2. 2.
    Seo, M., Urteaga, M., et al. (2011). A 300 GHz PLL in an InP HBT technology. In IEEE IMS (pp. 1–4).Google Scholar
  3. 3.
    Wu, C.-Y., Chen, M.-C., et al. (2009). A phase-locked loop with injection-locked frequency multiplier in 0.18-µm CMOS for V-band applications. IEEE Transactions on Microwave Theory and Techniques, 57(7), 1629–1636.CrossRefGoogle Scholar
  4. 4.
    Jain, S., & Belostotski, L. (2019). A 167-to-172 GHz 65-nm CMOS body-voltage-tuned harmonic-mode VCO. Microwave and Optical Technology Letters, 61, 546–549.CrossRefGoogle Scholar
  5. 5.
    Chiang, P.-H., Cheng, J.-H., Wu, Y.-C., Chiong, C.-C., Liu, W.-D., Huang, G.-W., Huang, T.-W., & Wang, H. (2015). A 206 ∼ 220 GHz CMOS VCO using body-bias technique for frequency tuning. In IEEE IMS (pp. 1–3).Google Scholar
  6. 6.
    Chiang, P.-Y., Wang, Z., et al. (2014). A 300 GHz frequency synthesizer with 7.9% locking range in 90 nm SiGe BiCMOS. In ISSCC (pp. 260–261).Google Scholar
  7. 7.
    Shahramian, S., Hart, A., et al. (2011). Design of a dual W- and D-band PLL. IEEE Journal of Solid-State Circuits, 46(5), 1011–1022.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.University of CalgaryCalgaryCanada

Personalised recommendations