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A 171 GHz harmonic-mode PLL with − 14.2 dBm output power in 65 nm CMOS

  • Sanjeev Jain
  • Leonid BelostotskiEmail author
Mixed Signal Letter
  • 27 Downloads

Abstract

This letter presents a harmonic-mode PLL (H-PLL) that avoids additional multiplication, filtering, and amplification stages and thus results in an area-efficient implementation. A proof-of-concept 57.5-mW 65-nm CMOS PLL prototype operating at 171 GHz provides − 14.2 dBm output power and a spur level of − 67.5 dBc. The PLL is built with a varactor-free 2fO VCO, which is tuned by varying transistor intrinsic capacitances via MOS bulk voltages.

Keywords

Phase-locked loops mm-Wave PLL mm-Wave VCO 

Notes

Acknowledgements

The authors acknowledge support from Eyes High Postdoctoral Fellowship, University of Calgary, NSERC Discovery and Engage programs, Canada Research Chair program, and CMC Microsystems for subsidizing the chip fabrication. Special thanks go to Steven Durant from Virginia Diodes Inc. for support with measurements.

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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.University of CalgaryCalgaryCanada

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