Modified linear in dB, sub 0.2 dB gain-step CMOS programmable gain amplifier for ultrasound applications

  • Yarallah KoolivandEmail author
  • Yasser Rezaeiyan
  • Omid Shoaei
  • Shahin Jafarabadi-Ashtiani
  • Ali Moftakharzadeh
  • Mohsen Ahmadvand


New techniques for controlling the gain of a programmable gain amplifier (PGA) using an eight-bit digital word has been proposed in this paper. The output taps of the R–2R ladder network feed just the two Gm stages through the switches controlled by three MSB bits of the control word. The parasitic capacitance at the different taps has been reduced and equalized making the bandwidth of the PGA wider and the gain error more uniform over the entire control span. Two current banks composed of 32 current sources plus a 10 µA dummy current source, controlled by the five LSB bits of the digital control word, determine the tail currents of the Gm stages to set the PGA gain precisely linear in dB. Dummy current sources, however, have no effect on the gain of the PGA, they will prevent the transistors from turning OFF making the gain update rate faster. A differential PGA has been designed in a 0.18 µm–1.8 V-CMOS technology. The maximum gain error is less than 0.03 dB in different corner cases. At the maximum gain, the bandwidth and the input referred noise voltage of the PGA are 82 MHz and 4.1 nV/√Hz respectively, while the circuit draws just 4.8 mA current from the supply.


Class AB Current steering DAC Linear in dB PGA Mismatch Noise R–2R resistor ladder attenuator Transconductance Ultrasound 


  1. 1.
    Christensen, D. A. (1988). Ultrasonic bioinstrumentation. New York: Wiley.Google Scholar
  2. 2.
    Ismail, A., & Abidi, A. A. (2005). A 3.1- to 8.2-GHz zero-IF receiver and direct frequency synthesizer in 0.18-µm SiGe BiCMOS for mode-2 MB-OFDM UWB communication. IEEE Journal of Solid State Circuits and Systems, 40(12), 2573–2582.CrossRefGoogle Scholar
  3. 3.
    Liu, H., Zho, X., Boon, C. C., & He, X. (2015). Cell-based variable-gain amplifiers with accurate dB-linear characteristic in 0.18 µm CMOS technology. IEEE Journal of Solid State Circuits and Systems, 50(2), 586–596.CrossRefGoogle Scholar
  4. 4.
    Kang, S. Y., Ryu, S. T., & Park, C. S. (2012). A precise decibel-linear programmable gain amplifier using a constant current-density function. IEEE Transactions on Microwave Theory and Techniques, 60(9), 2843–2850.CrossRefGoogle Scholar
  5. 5.
    Choi, I., Seo, H., & Kim, B. (2013). Accurate dB-linear variable gain amplifier with gain error compensation. IEEE Journal of Solid-State Circuits, 48(2), 456–464.CrossRefGoogle Scholar
  6. 6.
    Duong, Q.-H., Quan, L., & Lee, S.-G. (2005). An all CMOS 84-dB linear low-power variable gain amplifier. In IEEE symposium on VLSI circuits digest (pp. 114–117).Google Scholar
  7. 7.
    Elwan, H., Tekin, A., & Pedrotti, K. (2009). A differential-ramp based 65 dB linear VGA technique in 65 nm CMOS. IEEE Journal of Solid State Circuits and Systems, 44(9), 2503–2514.CrossRefGoogle Scholar
  8. 8.
    Elwan, H. O., & Ismail, M. (2000). Digitally programmable decibel-linear CMOS VGA for low-power mixed-signal applications. IEEE Transactions on Circuits Systems II: Analog Digital Signal Process, 47(5), 388–398.CrossRefGoogle Scholar
  9. 9.
    Gilbert, B. (1991). A low-noise wideband variable-gain amplifier using an interpolated ladder attenuator. ISSCC Dig. Tech. Papers (pp. 280–281).Google Scholar
  10. 10.
    El-Shennawy, M., Joram, N., & Ellinger, F. (2016). A 55 dB range gain interpolating variable gain amplifier with improved offset cancellation. In Proceedings of the PRIME.Google Scholar
  11. 11.
    El-Shennawy, M., Joram, N., & Ellinger, F. (2015). Techniques for maximizing input handling and improving linearity of gain interpolating VGAs. In Proceedings of the PRIME (pp. 1–4).Google Scholar
  12. 12.
  13. 13.
    Koolivand, Y., Shoaei, O., & Ashtiani, S. J. (2017). Linear in dB, sub 0.2 dB gain-step CMOS programmable gain amplifier for ultrasound applications. An International Journal of Analog Integrated Circuits and Signal Processing, 93(2), 309–318.CrossRefGoogle Scholar
  14. 14.
    Wu, R., Makinwa, K. A. A., & Huijsing, J. H. (2009). A chopper current-feedback instrumentation amplifier with a 1 mHz 1/f noise corner and an AC-coupled ripple reduction loop. IEEE Journal of Solid State Circuits and Systems, 44(12), 3232–3243.CrossRefGoogle Scholar
  15. 15.
    Pelgrom, M., Duinmaijer, A., & Welbers, A. (1989). Matching properties of MOS transistors. IEEE Journal of Solid-State Circuits, 24, 1433–1439.CrossRefGoogle Scholar
  16. 16.
    Kinget, P. R. (2005). Device mismatch and tradeoffs in the design of analog circuits. IEEE Journal of Solid-State Circuits, 40(6), 1212–1224.CrossRefGoogle Scholar
  17. 17.
    Razavi, B. (2001). Design of analog CMOS integrated circuits. New York: McGraw-Hill.Google Scholar
  18. 18.
    Maloberty, F. (2007). Data converters. Dordrecht: Springer.Google Scholar

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© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Nano-Electronic Center of Excellence, School of ECEUniversity of TehranTehranIran
  2. 2.Department of Electrical EngineeringYazd UniversityYazdIran
  3. 3.Department of Computer EngineeringHamadan University of TechnologyHamadanIran

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