2+2 MASH incremental ADC
- 18 Downloads
In this paper, 2+2 multi-stage noise shaping incremental ΔΣ ADC for wideband and high accuracy application is described and analyzed. The modulator introduced inter-stage gain to reduce the quantization noise without adding any hardware. Also, a gain scaling technique was used to decrease the power consumption by reducing the integrators’ output swing. A proof-of-concept prototype was fabricated with 0.18 μm 2P4M CMOS process. It achieved a 94.2 dB dynamic range and 74.8 dB SNDR in the 1.25 MHz signal band. The total power consumption is 67.1 mW with dual power supplies (analog 3.3 V, digital 1.8 V).
KeywordsMASH Incremental ΔΣ ADC Inter-stage gain Quantization noise Gain scaling technique
This research was supported by the Daegu University Research Grant, 20180396.
- 2.Schreier, R., & Temes, G. C. (2005). Understanding of delta-sigma data converters. New York: Wiley.Google Scholar