Design and optimization of CMOS glitch-free frequency-to-voltage converter for frequency-locked loop at GHz ranges
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In this letter, a new frequency-to-voltage converter based on the capacitors charge redistribution technique is proposed. By adding a capacitor in the charging tank, the proposed design overcomes the output glitches in the conventional converter while maintaining a high speed and small silicon area. Moreover, the output voltage is accumulated periodically without the voltage drop that potentially induces a stable issue. As a design example, the proposed converter is integrated into a prototype frequency locked loop fabricated in a standard 0.13 μm CMOS technology, occupying a core silicon area of 470 μm × 350 μm. Measurement results show that the proposed design is able to work at 651 MHz with the phase noise of − 124dBc/Hz@1 MHz while consuming 26.4 mW from a 1.2 V power supply.
KeywordsCharge redistribution CMOS integrated circuit Frequency-to-voltage converter Frequency locked loops Phase locked loops
This work was supported by National Natural Science Foundation of China under Grant Numbers 61574125 and U1709221, and the industry innovation Project of Suzhou City of China (No. SYG201641).
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