Analog Integrated Circuits and Signal Processing

, Volume 98, Issue 1, pp 221–232 | Cite as

A low-power and area-efficient quaternary adder based on CNTFET switching logic

  • Shirin Fakhari
  • Narges Hajizadeh Bastani
  • Mohammad Hossein MoaiyeriEmail author
Mixed Signal Letter


Due to the increasing short channel effects in scaled CMOS circuits, the need for alternative technologies has substantially been increased. Moreover, the limitation in space consumed by interconnects and increased power density in nanoscale binary circuits have challenged the scaling process to achieve more efficient and denser circuits. Accordingly, designing efficient nanoscale multiple-valued circuits is of great importance. In this paper, a low-power and area-efficient quaternary adder based on CNTFET switching logic is proposed. The proposed design significantly reduces the number of transistors, area and power consumption, while maintaining output driving capability and full swing operation. The proposed design is comprehensively simulated using HSPICE and the Stanford CNTFET model. Furthermore, the layout of the proposed circuit is drawn using the physical design tool for CNTFET-based circuits. The results confirm significant improvements regarding of area, average power consumption, PDP, static power dissipation and sensitivity to process variations compared to its state-of-the-art counterparts. Also, the proposed quaternary full adder is exerted as the building block of a 4-digit quaternary ripple carry adder, and the simulation results indicate its superiority regarding of energy efficiency.


Nanoelectronics CNTFET Quaternary logic Switching logic Full adder Multiple-valued logic (MVL) Nanotechnology 


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© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Faculty of Electrical EngineeringShahid Beheshti University, G.C.TehranIran
  2. 2.Department of Computer Engineering, Yadegar-e-Imam Khomeini (RAH) Shahre Rey BranchIslamic Azad UniversityTehranIran

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