Advertisement

A 20 GHz subharmonic injection-locked clock multiplier with mixer-based injection timing control in 65 nm CMOS technology

  • Fangxu Lv
  • Xuqiang Zheng
  • Jianye Wang
  • Guoli Zhang
  • Ziqiang Wang
  • Shuai Yuan
  • Yajun He
  • Chun Zhang
  • Zhihua Wang
Article
  • 22 Downloads

Abstract

This paper presents a 20 GHz subharmonic injection-locked clock multiplier (SILCM), which adopts a mixer based self-align injection timing control loop to guarantee the optimal injection point. In addition, to further improve the injection time accuracy and reduce the super, a V/I mismatch cancellation are utilized. Furthermore, a frequency-locked loop with a frequency-lock detection and enable control switch is employed to expand the injection-locked range and save power. Fabricated in a 65 nm CMOS technology, the SILCM can lock from 19.2 GHz to 23.2 GHz. It exhibits − 125.5 dBc/Hz phase noise at 1 MHz offset and consumes 8 mW under 1.2 V power supply. The measured root-mean-square jitter integrating from 0.1 kHz to 100 MHz is 106 fs and the reference spur is − 43 dB.

Keywords

Sub-harmonic injection-locked Injection timing control loop Phase noise Mixer Low power 

Notes

Acknowledgements

This work is supported by National Science Technology Major Project (No. 2016ZX01012101).

References

  1. 1.
    Zheng, X. Q., et al. (2016). A 5–50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS. In IEEE ESSCIRC Digest of Technical Papers (pp. 305–308), Sept. 2016.Google Scholar
  2. 2.
    Lee, J., et al. (2015). Design of 56 Gb/s NRZ and PAM4 SerDes transceivers in CMOS technologies. IEEE Journal of Solid-State Circuits, 50(9), 2061–2073.CrossRefGoogle Scholar
  3. 3.
    Helal, B. M., et al. (2009). A low jitter programmable clock multiplier based on a pulse injection-locked oscillator with a highly-digital tuning loop. IEEE Journal of Solid-State Circuits, 44(x), 1391–1400.CrossRefGoogle Scholar
  4. 4.
    Ali, T. A., et al. (2011). A 4.6 GHz MDLL with − 46 dBc reference spur and aperture position tuning. In IEEE ISSCC Digest of Technical Papers (pp. 466–468), Feb. 2011.Google Scholar
  5. 5.
    Helal, B. M., et al. (2008). A highly digital MDLL-based clock multiplier that leverages a self-scrambling time-to-digital converter to achieve subpicosecond jitter performance. IEEE Journal of Solid-State Circuits, 43(x), 855–863.CrossRefGoogle Scholar
  6. 6.
    Farjad-Rad, R., et al. (2002). A 0.2–2 GHz 12 mW multiplying DLL for low-jitter clock synthesis in highly-integrated data-communication chips. In IEEE ISSCC Digest of Technical Papers (pp. 56–57), Feb. 2002.Google Scholar
  7. 7.
    Gao, X., et al. (2009). A 2.2 GHz 7.6 mW sub-sampling PLL with − 126 dBc/Hz in-band phase noise and 0.15 ps RMS Jitter in 0.18 μm CMOS. In IEEE ISSCC Digest of Technical Papers (pp. 392–393), Feb. 2009.Google Scholar
  8. 8.
    Liang, C. F., & Hsiao, K. J. (2011). An injection-locked ring PLL with self-aligned injection window. In IEEE ISSCC Digest of Technical Papers (pp. 90–92), Feb. 2011.Google Scholar
  9. 9.
    Ye, S., et al. (2002). A multiple-crystal interface PLL with VCO realignment to reduce phase noise. IEEE Journal of Solid-State Circuits, 37(x), 1795–1803.Google Scholar
  10. 10.
    Lee, J., & Wang, H. (2009). Study of subharmonically injection-locked PLLs. IEEE Journal of Solid-State Circuits, 44(x), 1539–1553.CrossRefGoogle Scholar
  11. 11.
    Elkholy, A., et al. (2015). A 6.75-to-8.25 GHz 2.25 mW 190 fs rms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65 nm CMOS. In IEEE ISSCC Digest of Technical Papers (pp. 22–26), Feb. 2015.Google Scholar
  12. 12.
    Musa, A., et al. (2014). A compact, low-power and low-jitter dual-loop injection blocked PLL using all-digital PVT calibration. IEEE Journal of Solid-State Circuits, 49(1), 50–60.MathSciNetCrossRefGoogle Scholar
  13. 13.
    Ting Le, I., et al. (2013). A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing. In IEEE ISSCC Digest of Technical Papers (pp. 414–415), Feb. 2013.Google Scholar
  14. 14.
    Huang, K., et al. (2014). 2 GHz sub-harmonically injection-locked PLL with mixer-based injection timing control in 0.18 μm CMOS technology. IET Electronics Letters, 50(14), 855–857.CrossRefGoogle Scholar
  15. 15.
    Gao, X., et al. (2009). Jitter analysis and a benchmarking figure-of-merit for phase-locked loops. IEEE Transactions on Circuits and Systems II: Regular Papers, 56(2), 117–121.CrossRefGoogle Scholar
  16. 16.
    Huang, Y.-C. , & Liu, S.-I. (2012). A 2.4 GHz sub-harmonically injection-locked PLL with self-calibrated injection timing. In IEEE ISSCC Digest of Technical Papers (pp. 338–339), Feb. 2012.Google Scholar
  17. 17.
    Gao, X., et al. (2010). A 2.2 GHz sub-sampling PLL with 0.16 ps RMS jitter and − 125 dBc/Hz in-band phase noise at 700 μW loop-components power. In IEEE Symposium on VLSI Circuits Digest of Technical Papers (pp. 139–140), June 2010.Google Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  • Fangxu Lv
    • 1
    • 2
  • Xuqiang Zheng
    • 2
  • Jianye Wang
    • 1
  • Guoli Zhang
    • 1
  • Ziqiang Wang
    • 2
  • Shuai Yuan
    • 2
  • Yajun He
    • 2
  • Chun Zhang
    • 2
  • Zhihua Wang
    • 2
  1. 1.Air and Missile Defense CollegeAir Force Engineering UniversityXi’anChina
  2. 2.Institute of MicroelectronicsTsinghua UniversityBeijingChina

Personalised recommendations