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Analog Integrated Circuits and Signal Processing

, Volume 98, Issue 2, pp 277–289 | Cite as

Analysis of subthreshold SOI FinFET based two stage OTA for low power

  • Reena SonkusareEmail author
  • Prathamesh Milind Pilankar
  • Surendra S. Rathod
Article
  • 54 Downloads

Abstract

In this paper, subthreshold design and analysis of Silicon on Insulator Fin Field Effect Transistor (SOI FinFET) based two stage Operational Transconductance Amplifier (OTA) is presented for low power and low supply voltage in nanometre regime. The OTA design optimization is achieved by \(g_{m}/I_{D}\) methodology which helps to determine the device aspect ratios. Compactness is achieved by using nanometre FinFET technology. The OTA design is simulated using 30 nm SOI FinFET Berkeley Short-channel IGFET Common Multi-gate (BSIM-CMG) model, with bias current and supply voltage of 20 nA and \(\pm 0.5 V\);respectively. The simulation results in subthreshold regime of FinFET based two stage OTA has a gain of 57 dB with a phase margin of 69.81 degree, Common Mode Rejection Ratio (CMRR) of 61.55 dB and power consumption of 108 nW.

Keywords

SOI FinFET Subthreshold Low supply voltage OTA Gain CMRR Low Power dissipation 

References

  1. 1.
    Poiroux, T., Vinet, M., Faynot, O., Lolivier, J., Ernst, T., Previtali, B., et al. (2005). Multiple gate devices: Advantages and challenges. Micro Electronic Engineering, 80, 378–385.  https://doi.org/10.1016/j.mee.2005.04.095.CrossRefGoogle Scholar
  2. 2.
    Subramanian, V., Parvais, B., Borremans, J., Mercha, A., Linten, D., Wambacq, P, Loo, J., Dehan, M., Gustin, C., Collaert, N., Kubicek, S., Lander, R., Hooker, J., Cubaynes, F., Donnay, S., Jurczak, M., Groeseneken, G., Sansen, W., & Decoutere, S. (2006). Planar Bulk MOSFETs versus FinFETs: An Analog/RF Perspective, IEEE Transactions on Electron Devices.  https://doi.org/10.1109/TED.2006.885649.Google Scholar
  3. 3.
    Colinge, J.-P. (2004). Multiple-gate SOI MOSFETs. Solid-State Electronics, 48, 897–905.  https://doi.org/10.1016/j.sse.2003.12.020.CrossRefGoogle Scholar
  4. 4.
    Grasso, A. D., Pennisi, S., Scotti, G., & Trifiletti, A. (2017). 0.9-V class-AB Miller OTA in 0.35-m CMOS with threshold-lowered non-tailed differential pair. IEEE Transactions on Circuits and Systems-I Regular Papers.  https://doi.org/10.1109/TCSI.2017.2681964.Google Scholar
  5. 5.
    Grasso, A. D., Marano, D., Palumbo, G., & Pennisi, S. (2015). Design methodology of subthreshold three-stage CMOS OTAs suitable for ultra-low-power low-area and high driving capability. IEEE Transactions on Circuits and Systems-I Regular Papers.  https://doi.org/10.1109/TCSI.2015.2411796.MathSciNetGoogle Scholar
  6. 6.
    Ferreira, L. H. C. , & Sonkusale, S. R. (2014). A 60-dB gain OTA operating at 0.25-V power supply in 130-nm digital CMOS process, IEEE Transactions on Circuits and Systems-I Regular Papers.  https://doi.org/10.1109/TCSI.2013.2289413.Google Scholar
  7. 7.
    Sutula, S., Dei, M., Teres, L., & Serra-Graells, F. (2016). Variable-mirror amplifier: A new family of process-independent class-ab single-stage OTAs for low-power SC circuits. IEEE Transactions on Circuits and Systems-I Regular Papers.  https://doi.org/10.1109/TCSI.2016.2577838.MathSciNetGoogle Scholar
  8. 8.
    Abdelfattah, O., Roberts, G. W., Shih, I., & Shih, Y.-C. (2015). An ultra-low-voltage CMOS process-insensitive self-biased OTA with rail-to-rail input range. IEEE Transactions on Circuits and Systems-I Regular Papers.  https://doi.org/10.1109/TCSI.2015.2469011.MathSciNetGoogle Scholar
  9. 9.
    Marano, D., Grasso, A. D., Palumbo, G., & Pennisi, S. (2016). Optimized active single-miller capacitor compensation with inner half-feedforward stage for very high-load three-stage OTAs. IEEE Transactions on Circuits and Systems-I Regular Papers.  https://doi.org/10.1109/TCSI.2016.2573920.MathSciNetGoogle Scholar
  10. 10.
    Grasso, A. D., Palumbo, G., & Pennisi, S. (2016). High-performance four-stage CMOS OTA suitable for large capacitive loads. IEEE Transactions on Circuits and Systems-I Regular Papers.  https://doi.org/10.1109/TCSI.2015.2476298.Google Scholar
  11. 11.
    International technology road map for semiconductors (ITRS), 2013 edition, and executive summary. Available: http://www.itrs.net/
  12. 12.
    Kawasaki, H., Khate, M., Guillorn, J. M., Fuller, N., Chang, J., Kanakasabapathy, S., Chang, L., Murlidhar, R., Babich, K., Yang, Q., Ott, J., Klaus, D., Kratschmer, E., Sikorski, E., Miller, R., Viswanathan, R., Zhang, Y., Silverman, J., Ouyang, Q., Yagishita, A., Haensch, W., & Ishimaru, K. (2008). Demonstration of highly scaled FinFET SRAM cells with high-k/metal gate and investigation of characteristic variability for the 32 nm node and beyond. In IEEE international conference on electron devices meeting, Dec 2008.  https://doi.org/10.1109/IEDM.2008.4796661.
  13. 13.
    Hisamoto, D., Lee, W.-C., Kedzierski, J., Takeuchi, H., Asano, K., Kuo, C., et al. (2000). FinFET-a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Transactions on Electron Devices, 47(12), 2320–2325.CrossRefGoogle Scholar
  14. 14.
    Liaw, Y.-G., Liao, W.-S., Wang, M.-C., Lin, C.-L., Zhou, B., Gu, H., et al. (2016). A high aspect ratio silicon-fin FinFET fabricated upon SOI wafer. Solid State Electronics.  https://doi.org/10.1016/j.sse.2016.09.017.Google Scholar
  15. 15.
    Pei, G., Kedzierski, J., Oldiges, P., Ieong, M., & Kan, E. C.-C. (2002). FinFET design considerations based on 3-D simulation and analytical modeling. IEEE Transaction on Electron Devices.  https://doi.org/10.1109/TED.2002.801263.Google Scholar
  16. 16.
    Huang, X, Lee, W-C, Kuo, C., Hisamoto, D., Chang, L, Kedzierski, J., Anderson, E., Takeuchi, H., Choi, Y.-K., Asano, K., Subramanian, V., King, T-J, Bokor, J., & Hu, C. (2001). Sub-50 nm p-channel FinFET, IEEE Transactions on Electron Devices.  https://doi.org/10.1109/16.918235 Google Scholar
  17. 17.
    Rathod, S. S., Saxena, A. K., & Dasgupta, S. (2011). Modelling of threshold voltage, mobility, drain current and subthreshold leakage current in virgin and irradiated silicon-on-insulator fin-shaped field effect transistor device. Journal of Applied Physics, 108, 084504.  https://doi.org/10.1063/1.3553836.CrossRefGoogle Scholar
  18. 18.
    Es-Sakhi, A., & Chowdhury, M. (2017). Analysis of device capacitance and subthreshold behavior of Tri-gate SOI FinFET. Microelectronics Journal, 62, 30–37.  https://doi.org/10.1016/j.mejo.2017.02.005.CrossRefGoogle Scholar
  19. 19.
    Ragheb, A. N., & Kim, H. W. (2017). Ultra-low power OTA based on bias recycling and subthreshold operation with phase margin enhancement. Microelectronics Journal, 60, 94–101.  https://doi.org/10.1016/j.mejo.2016.12.007.CrossRefGoogle Scholar
  20. 20.
    Elamien, M. B., & Mahmoud, S. A. (2017). Analysis and design of a highly linear CMOS OTA for portable biomedical applications in 90 nm CMOS. Microelectronics Journal, 70, 72–80.  https://doi.org/10.1016/j.mejo.2017.10.009.CrossRefGoogle Scholar
  21. 21.
    Allen, P. E., & Holberg, D. R. (2016). CMOS analog circuit design. New Delhi: Oxford University Press.Google Scholar
  22. 22.
    Nandi, A., Saxena, A. K., & Dasgupta, S. (2016). Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET. Microelectronics Journal.  https://doi.org/10.1016/j.mejo.2016.05.014.Google Scholar
  23. 23.
    Thakker, R. A., Srivastava, M., Tailor, K. H., Baghini, M. S., Sharma, D. K., Rao, V. R., et al. (2011). A novel architecture for improving slew rate in FinFET-based op-amps and OTAs. Microelectronics Journal.  https://doi.org/10.1016/j.mejo.2011.01.010.Google Scholar
  24. 24.
    Sonkusare, R, Pilankar, P., Saini, A., & Rathod, S. S. (2017). Design of SOI FinFET based two stage operational transconductance amplifier, IEEE VLSI Circuits and Systems Letter, 3(3), 26–37.Google Scholar
  25. 25.
    Razavi, B. (1999). CMOS technology characterization for analog and RF design. IEEE Journal of Solid-State Circuits., 34(3), 268–276.  https://doi.org/10.1109/4.748177.CrossRefGoogle Scholar
  26. 26.
    Rahin, V., & Rahin, A. (2016). A low-voltage and low-power two-stage operational amplifier using FinFET transistors. International Academic Journal of Science and Engineering, 3(4), 80–95.Google Scholar
  27. 27.
    Lundager, K., Zeinali, B., Tohidi, M., Madsen, J. K., & Moradi, F. (2016). Low power design for future wearable and implantable devices. Journal of Low Power Electronics and Applications, 6(4), 2016.  https://doi.org/10.3390/jlpea6040020.CrossRefGoogle Scholar
  28. 28.
    Liu, L., Song, Y., Mu, J., Guo, W., Zhu, Z., & Yang, Y. (2017). A high accuracy CMOS subthreshold voltage reference with offset cancellation and thermal compensation. Microelectronics Journal, 60, 102–108.  https://doi.org/10.1016/j.mejo.2016.12.006.CrossRefGoogle Scholar
  29. 29.
    Sharan, T., & Bhadauria, V. (2016). Sub-threshold, cascade compensated, bulk-driven OTAs with enhanced gain and phase-margin. Microelectronics Journal, 54, 150–165.  https://doi.org/10.1016/j.mejo.2016.05.009.CrossRefGoogle Scholar
  30. 30.
    Olejarz, P., Park, K., MacNaughton, S., Dokmeci, M. R., & Sonkusale, S. (2012). 0.5 \(\mu\)W sub-threshold operational transconductance amplifiers using 0.15 \(\mu\)m fully depleted silicon-on-insulator (FDSOI) process. Journal of Low Power Electronics and Applications, 2, 155–167.CrossRefGoogle Scholar
  31. 31.
    Magnelli, L., Amoroso, F. A., Crupi, F., Cappuccino, G., & Iannaccone, G. (2012). Design of a 75nW, 0.5V subthreshold complementary metal-oxide-semiconductor operational amplifier, International Journal of Circuit Theory and Applications.  https://doi.org/10.1002/cta.1898.Google Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  • Reena Sonkusare
    • 1
    Email author
  • Prathamesh Milind Pilankar
    • 2
  • Surendra S. Rathod
    • 1
  1. 1.Sardar Patel Institute of TechnologyMumbaiIndia
  2. 2.Indian Institute of Technology BombayMumbaiIndia

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