Analog Integrated Circuits and Signal Processing

, Volume 98, Issue 2, pp 277–289 | Cite as

Analysis of subthreshold SOI FinFET based two stage OTA for low power

  • Reena SonkusareEmail author
  • Prathamesh Milind Pilankar
  • Surendra S. Rathod


In this paper, subthreshold design and analysis of Silicon on Insulator Fin Field Effect Transistor (SOI FinFET) based two stage Operational Transconductance Amplifier (OTA) is presented for low power and low supply voltage in nanometre regime. The OTA design optimization is achieved by \(g_{m}/I_{D}\) methodology which helps to determine the device aspect ratios. Compactness is achieved by using nanometre FinFET technology. The OTA design is simulated using 30 nm SOI FinFET Berkeley Short-channel IGFET Common Multi-gate (BSIM-CMG) model, with bias current and supply voltage of 20 nA and \(\pm 0.5 V\);respectively. The simulation results in subthreshold regime of FinFET based two stage OTA has a gain of 57 dB with a phase margin of 69.81 degree, Common Mode Rejection Ratio (CMRR) of 61.55 dB and power consumption of 108 nW.


SOI FinFET Subthreshold Low supply voltage OTA Gain CMRR Low Power dissipation 


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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  • Reena Sonkusare
    • 1
    Email author
  • Prathamesh Milind Pilankar
    • 2
  • Surendra S. Rathod
    • 1
  1. 1.Sardar Patel Institute of TechnologyMumbaiIndia
  2. 2.Indian Institute of Technology BombayMumbaiIndia

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