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Analog Integrated Circuits and Signal Processing

, Volume 98, Issue 2, pp 257–264 | Cite as

A two-stage CMOS OTA with enhanced transconductance and DC-gain

  • Boran Wen
  • Qisheng ZhangEmail author
  • Xiao Zhao
Article
  • 127 Downloads

Abstract

An ultra-low-power process-insensitive two-stage OTA working in weak inversion region with enhanced transconductance and DC gain is presented in this paper. The proposed two-stage OTA is based on a bulk-driven input stage with rail-to-rail input voltage range, in which the bulk transconductance is enhanced by means of a partial positive-feedback loop. At the same time, a pseudo-cascode frequency compensation technique is applied in this design to improve the phase margin and accordingly, robust the stability of the proposed OTA. In addition, the proposed composite-transistor structure is used to improve output impedance of the two-stage OTA in weak inversion region. As a result, the improvement of DC gain and gain-bandwidth is obtained. Transistor-level simulations and results in UMC 0.18 \(\upmu \hbox {m}\) CMOS process confirm the theoretical results. Simulated from a 0.5 V supply voltage, the proposed two-stage OTA achieves a 111.5 dB DC gain, a gain-bandwidth product of 9.5 kHz and a phase-margin of \(66^{\circ }\) while driving a 15 pF load.

Keywords

Two-stage OTA Bulk-driven Transconductance improvement DC gain enhancement Frequency compensation Ultra-low-power 

Notes

Acknowledgements

This work is supported by the National Natural Science Foundation of China (No. 41704174) and the National Nature Science Foundation of China (No. 41574131).

References

  1. 1.
    Zuo, L., & Islam, S. K. (2013). Low-voltage bulk-driven operational amplifier with improved transconductance. IEEE Transactions on Circuits and Systems I: Regular Papers, 60(8), 2084–2091.CrossRefGoogle Scholar
  2. 2.
    Park, Y.-I., Karthikeyan, S., Tsay, F., & Bartolome, E. (2001). A low power 10 bit, 80 MS/sCMOS pipelined ADC at 1. 8 V power supply. In IEEE International Solid State Circuits Conference (pp. 580–583).Google Scholar
  3. 3.
    Ferreira, L. H. C., & Sonkusale, S. R. (2014). A 60-dB gain OTA operating at 0.25-V power supply in 130-nm digital CMOS process. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(6), 1609–1617.CrossRefGoogle Scholar
  4. 4.
    Cotrim, E. D. C., & Ferreira, L. H. C. (2012). An ultra-low-power CMOS symmetrical OTA for low-frequency \(G_m-C\) applications. Analog Integrated Circuits Signal Process, 71(2), 275–282.CrossRefGoogle Scholar
  5. 5.
    Chatterjee, S., Tsividis, Y., & Kinget, P. (2005). 0.5-V analog circuit techniques and their application in OTA and filter design. IEEE Journal of Solid-State Circuits, 40(12), 2372–2387.CrossRefGoogle Scholar
  6. 6.
    Ferreira, L. H. C., Pimenta, T. C., & Moreno, R. L. (2007). An ultra-low-voltage ultra-low-power CMOS miller OTA with rail-to-rail input/output swing. IEEE Transactions on Circuits and Systems II: Express Briefs, 54(10), 843–847.CrossRefGoogle Scholar
  7. 7.
    Carrillo, J. M., Torelli, G., Valverde, R. P. A., & Duque-Carrillo, J. F. (2007). 1-V rail-to-rail CMOS opamp with improved bulk-driven input stage. IEEE Journal of Solid-State Circuits, 42(3), 508–517.CrossRefGoogle Scholar
  8. 8.
    Ahuja, B. K. (1983). An improved frequency compensation technique for CMOS operational amplifiers. IEEE Journal of Solid-State Circuits, 18(6), 629–633.CrossRefGoogle Scholar
  9. 9.
    Hurst, P. J., Lewis, S. H., Keane, J. P., Aram, F., & Dyer, K. C. (2004). Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers. IEEE Transactions on Circuits and Systems I, 51(2), 275–285.CrossRefzbMATHGoogle Scholar
  10. 10.
    Yoshizawa, A., & Tsividis, Y. (2007). A channel-select filter with agile blocker detection andadaptive power dissipation. IEEE Journal of Solid-State Circuits, 42(5), 1090–1099.CrossRefGoogle Scholar
  11. 11.
    You, F., Embabi, S. H. K., & Sanchez-Sinencio, E. (1997). A multistage amplifier topology with nested \(\text{G}_{\text{m}}-\text{C}\) compensation. IEEE Journal of Solid-State Circuits, 32(12), 2000–2011.CrossRefGoogle Scholar
  12. 12.
    Annema, A., Nauta, B., Langevelde, R. V., & Tuinhout, H. (2005). Analog circuits in ultra-deep-submicron CMOS. IEEE Journal of Solid-State Circuits, 40(1), 132–143.CrossRefGoogle Scholar
  13. 13.
    Chakraborty, S., Mallik, A., Sarkar, C. K., & Rao, V. R. (2007). Impact of halo doping on the sub-threshold performance of deep-submicrometer CMOS devices and circuits for ultra-low power analog/mixed-signal applications. IEEE Transactions on Electron Devices, 54(2), 241–248.CrossRefGoogle Scholar
  14. 14.
    Galup-Montoro, C., Schneider, M. C., & Loss, I. J. B. (1994). Series-parallel association of FETs for high gain and high frequency applications. IEEE Journal of Solid-State Circuits, 29(9), 1094–1101.CrossRefGoogle Scholar
  15. 15.
    Ferreira, L. H. C., & Sonkusale, S. R. (2012) \(G_m\) enhancement for bulk driven sub-threshold differential pair in nanometer CMOS process. In Subthreshold microelectronics conference (Vol. 13).Google Scholar
  16. 16.
    Sharan, T., & Bhadauria, V. (2016). Sub-threshold, cascode compensated, bulk-driven OTAs with enhanced gain and phase-margin. Microelectronics Journal, 54, 150–165.CrossRefGoogle Scholar
  17. 17.
    Carrillo, J. M., Torelli, G., & Valverde, P. A. (2007). 1-V rail-to-rail CMOS OpAmp with improved bulk-driven input stage. IEEE Journal of Solid-State Circuits, 42(3), 508–517.CrossRefGoogle Scholar
  18. 18.
    Zuo, L., & Islam, S. K. (2013). Low-voltage bulk-driven operational amplifier with improved transconductance. IEEE Transactions on Circuits & Systems I Regular Papers, 60(8), 2084–2091.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.School of Geophysics and Information TechnologyChina University of Geosciences (Beijing)BeijingPeople’s Republic of China

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