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Analog Integrated Circuits and Signal Processing

, Volume 98, Issue 1, pp 109–123 | Cite as

A resistive DAC for a multi-stage sigma-delta modulator DAC with dynamic element matching

  • Astria Nur IrfansyahEmail author
  • Torsten Lehmann
  • Julian Jenkins
  • Tianle Tong
  • Tara Julia Hamilton
Article
  • 145 Downloads

Abstract

This paper presents a study and implementation of a shunt–shunt resistive voltage divider digital-to-analog converter (DAC) for use as a multibit DAC in a multi-stage noise shaping sigma-delta modulator DAC design with dynamic element matching. This resistive DAC structure is employed to address the problem of code-dependent finite output impedance and thus aims to improve systematic linearity, while still being suitable for scaled CMOS processes. Chip measurement results from an implementation in CMOS 180 nm technology are presented. At low sampling clock frequencies, an SFDR of 71.81 dB is achieved, while at a higher sampling clock frequency of 600 MHz the SFDR is measured to be 59.73 dB, all for an OSR of 32. Our results show that low systematic nonlinearity can be achieved with this resistive DAC at low sampling frequencies, and we discuss potential enhancements to our prototype to obtain better SFDR at higher sampling rate.

Keywords

DAC Dynamic element matching MASH Sigma-delta 

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© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Institut Teknologi Sepuluh NopemberSurabayaIndonesia
  2. 2.University of New South WalesSydneyAustralia
  3. 3.Perceptia Devices Australia Pty. Ltd.SydneyAustralia
  4. 4.MARCS InstituteWestern Sydney UniversitySydneyAustralia

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