A 12-Gb/s HDMI 2.1 quarter-rate transmitter in 28-nm bulk CMOS process
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A four-lane 12-Gb/s per lane high-definition multimedia interface (HDMI) 2.1 transmitter is developed in 28-nm bulk CMOS process. To relieve the burden of the generation and distribution of clock, quarter-rate architecture is employed where the duty-cycle and phase spacing errors of multi-phase clock are automatically corrected by analog–digital converter based digital logic. The output driver terminated with 3.3-V supply is implemented only with 1.8- and 1.0-V transistors which are protected from over-voltage stress by double-cascoding with adaptive bias generation. The 4-lane HDMI 2.1 transmitter consumes 12.0-mW/lane at 12-Gb/s and occupies 0.12-mm2 active area.
KeywordsHigh-definition multimedia interface (HDMI) Transmitter Quarter-rate Driver CMOS
A part of this work was supported by the MOTIE (Ministry of Trade, Industry & Energy) (10080285) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device and the authors would like to thank the engineering staffs of Alpha Solutions Inc. for their support of this work.
Funding was provided by the Institute for Information & communications Technology Promotion (IITP) grant funded by the Korea government (MSIP) (Grant No. R7119-16-1009).
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