A 12-Gb/s HDMI 2.1 quarter-rate transmitter in 28-nm bulk CMOS process
- 64 Downloads
A four-lane 12-Gb/s per lane high-definition multimedia interface (HDMI) 2.1 transmitter is developed in 28-nm bulk CMOS process. To relieve the burden of the generation and distribution of clock, quarter-rate architecture is employed where the duty-cycle and phase spacing errors of multi-phase clock are automatically corrected by analog–digital converter based digital logic. The output driver terminated with 3.3-V supply is implemented only with 1.8- and 1.0-V transistors which are protected from over-voltage stress by double-cascoding with adaptive bias generation. The 4-lane HDMI 2.1 transmitter consumes 12.0-mW/lane at 12-Gb/s and occupies 0.12-mm2 active area.
KeywordsHigh-definition multimedia interface (HDMI) Transmitter Quarter-rate Driver CMOS
A part of this work was supported by the MOTIE (Ministry of Trade, Industry & Energy) (10080285) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device and the authors would like to thank the engineering staffs of Alpha Solutions Inc. for their support of this work.
Funding was provided by the Institute for Information & communications Technology Promotion (IITP) grant funded by the Korea government (MSIP) (Grant No. R7119-16-1009).
- 2.Rajagopal, K. (2012). Dynamically biased low power high performance 3.3 V output buffer in a single well bulk CMOS 1.8 V oxide 45 nm process. In Proceedings-international symposium. Quality electronic design (pp. 159–164).Google Scholar
- 3.Kim, H., Park, J., Han, W., Oh, K., Ahn, T., Jo, J.-G., & Yoo, C. (2016). A HDMI-to-MHL video format conversion system-on-chip (SoC) for mobile handset in a 130-nm CMOS technology. In Proceedings-IEEE international conference on consumer electronics (pp. 546–547).Google Scholar
- 4.HDMI [Online]. (2018). Available https://en.wikipedia.org/wiki/HDMI#cite_note-hdmi_2.1_pr-130. Accessed 10 Oct 2017.
- 7.Kim, J., Balankutty, A., Elshazly, A., Huang, Y.-Y., Song, H., Yu, K., & O’Mahony, F. (2016). A 16-to-40 Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14 nm CMOS. In Digest of technical papers-IEEE international. Solid-state circuits conference (pp. 60–61).Google Scholar
- 8.Choi, W.-S., Shu, G., Talegaonkar, M., Liu, Y., Wei, D., Benini, L., & Hanumolu, P. K. (2015). A 0.45-to-0.7 V 1-to-6 Gb/s 0.29-to-0.58 pJ/b source synchronous transceiver using automatic phase calibration in 65 nm CMOS. In Digest of technical papers-IEEE international. Solid-state circuits conference. (pp. 66–67).Google Scholar
- 9.Kim, H., Kim, O., & Yoo, C. (2017). Duty-cycle and phase spacing error correction circuit for high-speed serial link. IEICE Electronics Express, 14(12), 1–7.Google Scholar