Springer Nature is making SARS-CoV-2 and COVID-19 research free. View research | View latest news | Sign up for updates

Effect of fringing field capacitances in RF and small signal parameters of surrounding gate MOSFET

  • 6 Accesses


A small signal equivalent model of surrounding gate MOSFET incorporating fringing capacitances has been proposed and detailed in this paper. Detail modeling of the fringing (outer and inner both) capacitances of surrounding gate MOSFETs are considered here. Considering fringing capacitance, also the gate to drain/source and effective gate capacitances have been calculated for the proposed model. Low frequency Y-parameters (admittance parameters) of the SRG MOSFET are derived from the proposed model and expressed using real/imaginary function for different biasing condition. RF/analog performance parameters like Gate input capacitance (CGG), transport time delay (τ), input resistance (Rin), trans-conductance (gm), channel conductance (gds) etc have been evaluated. Figure of Merit (FOM) parameters like cut off frequency, gmRo, maximum oscillation frequency etc of the proposed model has been evaluated to study the effect of parasitic capacitances on the RF performances in depth. Extensive simulations using Silvaco ATLAS have been done to verify the proposed models. Matching of the simulated results with the model data demonstrate the correctness of the proposed model. It has been observed that the fringing capacitances can deteriorate the ac characteristics of the nano dimensional surrounding/cylindrical gate MOSFET.

This is a preview of subscription content, log in to check access.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12


  1. An T, Kim S (2013) 3-D modeling of fringing gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs. In: 2013 International conference on simulation of semiconductor processes and devices (SISPAD), Glasgow, pp 256–259

  2. ATLAS (2003) ATLAS user’s manual, vols 1–2. Software version 5.6.0.R. Silvaco International, Sunnyvale

  3. Chian TK (2015) A new quasi-3D compact threshold voltage model for pi-gate (ΠG) MOSFETs with the interface trapped charges. IEEE Trans Nanotechnol 14(3):555–559

  4. Chiang T (2016) A new device-physics-based noise margin/logic swing model of surrounding-gate MOSFET working on subthreshold logic gate. IEEE Trans Electron Devices 63(11):4209–4217

  5. Cho S, Kim K, Park B, Kang I (2011) RF performance and small-signal parameter extraction of junctionless silicon nanowire MOSFETs. IEEE Trans Electron Devices 58(5):1388–1396

  6. Das R, Chakraborty S, Dasgupta A, Dutta A, Kundu A, Sarkar CK (2016) Analysis of high-k spacer on symmetric underlap DG-MOSFET with Gatestack architecture. Superlattices Microstruct 97:386–396

  7. Ghosh P, Haldar S, Gupta R, Gupta M (2012) An accurate small signal modeling of cylindrical/surrounded gate MOSFET for high frequency applications. J Semicond Technol Sci. https://doi.org/10.5573/JSTS.2012.12.4.377

  8. Kim S-H, Fossum JG, Yang J-W (2006) Modeling and significance of fringing capacitance in nonclassical CMOS devices with gatesource/drain underlap. IEEE Trans Electron Devices 53(9):2143–2150

  9. Lee Y, Shin C (2017) Impact of equivalent oxide thickness on threshold voltage variation induced by work-function variation in multigate devices. IEEE Trans Electron Devices 64(5):2452–2456

  10. Liou JJ, Gao H, Wang Y, Chiang T (2018) A unified quasi-3D subthreshold behavior model for multiple-gatemosfets. IEEE Trans Nanotechnol 17(4):763–771

  11. Lu K, Dong Y, Yang W, Guo Y (2018) Body effects on the tuning RF performance of PD SOI technology using four-port network. IEEE Electron Device Lett 39(6):795–798

  12. McAndrew CC, Zaneski G, Layman PA, Ayyar SG (1994) Accurate characterization of MOSFET overlap/fringing capacitance for circuit design. In: Proceedings of IEEE ICMTS, pp 15–20

  13. Singh R et al (2018a) Evaluation of 10-nm bulk FinFET RF performance—conventional versus NC-FinFET. IEEE Electron Device Lett 39(8):1246–1249

  14. Singh J et al (2018b) 14-nm FinFET technology for analog and RF applications. IEEE Trans Electron Devices 65(1):31–37

  15. Suzuki K (1999) Parasitic capacitance of submicrometer MOSFET’s. IEEE Trans Electron Devices 46(9):1895–1900

  16. Tsividis P (1999) Operation and modelling of the MOS transistor. McGraw-Hill, New York

  17. Wu C-L, Yu C, Kenneth KO (2015) Amplification of nonlinearity in multiple-gate transistor millimeter wave mixer for improvement of linearity and noise margin. IEEE Microw Wirel Compon Lett 25(5):310–312

  18. Zou J, Xu Q, Luo J, Wang R, Huang R, Wang Y (2011) Predictive 3-D modeling of parasitic gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs. IEEE Trans Electron Devices 58(10):3379–3387

Download references

Author information

Correspondence to Rahul Das.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Ray, R., Das, R. & Chanda, M. Effect of fringing field capacitances in RF and small signal parameters of surrounding gate MOSFET. Microsyst Technol (2020). https://doi.org/10.1007/s00542-020-04765-1

Download citation