A 4 bit highly energy and area efficient SC SAR ADC based on a combinational technique with reduced reset energy
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A combinational method, based on hybrid and junction splitting techniques, is used to realize a 4 bit high energy efficient SC SAR ADC. The hybrid switching scheme is very energy efficient in which the first three comparison cycles do not consume any energy. In junction split technique, the total value of capacitors does not remain constant. Rather capacitors are appended as bits are being determined successively. The present method combines the features of these two methods to realize an even more energy efficient SC SAR ADC. Reset energy, in some cases, can seriously impact the overall efficiency of a SC SAR ADC. A study has been made about the normal reset energy and two step reset energy for the different cases. A table has been drawn to show the overall energy efficiency for normal conversion, conversion with single step reset and lastly conversion with two step reset for all the architectures.
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