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Microsystem Technologies

, Volume 25, Issue 12, pp 4615–4624 | Cite as

A power efficient PFD-CP architecture for high speed clock and data recovery application

  • Madhusudan Maiti
  • Suraj Kumar Saw
  • Vijay Nath
  • Alak MajumderEmail author
Technical Paper
First Online:
  • 137 Downloads

Abstract

This paper explores a speed and power improved dead zone free, low gate count CMOS phase frequency detector with charge pump (PFD-CP) for clock and data recovery application. Implemented in 90 nm CMOS technology, the proposed circuit configuration estimates a layout area of 420.66 μm2 and burns a low power as small as 172.10 μW when simulated with 5 GHz frequency at a power supply of 1.2 V at Cadence Virtuoso platform. With the elimination of reset path available in conventional PFD, this architecture doesn’t only become blind zone free, but it also offers a lower phase noise and output noise of − 142.46 dBc/Hz and − 131.145 dBc/Hz respectively at 1 MHz offset. We have also studied the performance metrics with skew and without skew at different extreme corners for schematic and post layout to manifest the variation awareness and robustness of the circuit. The scalability of the circuit arrangement is also endorsed at lower CMOS technology.

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Notes

Acknowledgements

We would like to thank MEITY (No. 9(1)/2014-MDD), Government of India for offering financial assistance under SMDP-C2SD project to carry out this work.

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Copyright information

© Springer-Verlag GmbH Germany, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Integrated Circuit and System (i-CAS) Lab, Department of Electronics and Communication Engineering (ECE)National Institute of TechnologyYupiaIndia
  2. 2.Department of Electronics and Communication EngineeringBirla Institute of TechnologyMesraIndia

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