Advertisement

A multi-step etch method for fabricating slightly tapered through-silicon vias based on modified Bosch process

  • Pengrong Lin
  • Xiaochen Xie
  • Yong Wang
  • Binhao Lian
  • Guoqi Zhang
Technical Paper
  • 14 Downloads

Abstract

In this paper, a multi-step etching method based on Bosch process was investigated to fabricate a slightly tapered via. The diameter of vias was scaled from 40 to 100 µm. Isotropic etching step was added into Bosch process to control the angle of the tapered vias. The slope angle could be adjusted by changing the time settings of isotropic etching step. The influence of the platen temperature was also studied. The passivation and etching steps are extremely sensitive to temperature. Silicon grass could be formed at low temperature. The two different processes of isotropic SF6 etching and Cl2/HBr etching were also compared. The wrinkles and cracks were observed on the surface after treatment with isotropic SF6 etching. The Cl2/HBr etching method is much better for removing the scallops.

Notes

Acknowledgements

This work was supported by Beijing Natural Science Foundation (Grant no. 4172065).

References

  1. Aachboun S et al (2000) Cryogenic etching of deep narrow trenches in silicon. J Vac Sci Technol A 18:1848–1852CrossRefGoogle Scholar
  2. Chen KS et al (2002) Effect of process parameters on the surface morphology and mechanical performance of silicon structures after DRIE. J Microelectromech Syst 11(3):264–275CrossRefGoogle Scholar
  3. Dixit P et al (2008) High aspect ratio vertical through-vias for 3D MEMs packaging applications by optimized three-step deep RIE. J Electrochem Soc 155(2):H85–H91CrossRefGoogle Scholar
  4. Dixit P et al (2012) Effect of process gases on fabricating tapered through-silicon vias by continuous SF6/O2/Ar plasma etching. J Solid State Sci Technol 1(3):P107–P116CrossRefGoogle Scholar
  5. International Technology Roadmap for Semiconductors (ITRS) (2011) Assembly and packaging, 2011 ednGoogle Scholar
  6. Jansen H et al (1995) The black silicon method: a universal method for determining the parameter setting of a fluorine-based reactive ion etcher in deep silicon trench etching with profile control. J Micromech Microeng 5:115–120CrossRefGoogle Scholar
  7. Jansen H et al (2009) The black silicon method X: a review on high speed and selective plasma etching of silicon with profile control: an in-depth comparison between Bosch and cryostat DRIE processes as a roadmap to next generation equipment. J Micromech Microeng 19:033001CrossRefGoogle Scholar
  8. Lärmer F, Schilp A (1996) Parents DE4241045, US 5501893 and EP 625285Google Scholar
  9. Li R et al (2008) Continuous deep reactive ion etching of tapered via holes for three-dimensional integration. J Micromech Microeng 18:125023CrossRefGoogle Scholar
  10. Lühn O et al (2008) Barrier and seed layer coverage in 3D structures with different aspect ratios using sputtering and ALD processes. Microelectron Eng 85:1947–1951CrossRefGoogle Scholar
  11. Marty F et al (2005) Advanced etching of silicon based on deep reactive ion etching for silicon high aspect ratio microstructures and three-dimensional micro- and nanostructures. Microelectron J 36:673–677CrossRefGoogle Scholar
  12. Ngo H et al (2006) Plasma etching of tapered features in silicon for MEMs and wafer level packaging applications. J Phys Conf Ser 34:271–276CrossRefGoogle Scholar
  13. Oehrlein GS et al (1990) Study of sidewall passivation and microscopic silicon roughness phenomena in chlorine-based reactive ion etching of silicon trenches. J Vac Sci Technol B 8:1199–1211CrossRefGoogle Scholar
  14. Roxhed N et al (2007) A method for tapered deep reactive ion etching using a modified Bosch process. J Micromech Microeng 17:1087–1092CrossRefGoogle Scholar
  15. Wu B et al (2010) High aspect ratio silicon etch: a review. J Appl Phys 108:051101CrossRefGoogle Scholar

Copyright information

© Springer-Verlag GmbH Germany, part of Springer Nature 2018

Authors and Affiliations

  • Pengrong Lin
    • 1
  • Xiaochen Xie
    • 1
  • Yong Wang
    • 1
  • Binhao Lian
    • 1
  • Guoqi Zhang
    • 2
  1. 1.Beijing Microelectronics Technology InstituteBeijingChina
  2. 2.Department of MicroelectronicsDelft University of TechnologyDelftThe Netherlands

Personalised recommendations