## Abstract

We consider the *Minimum Elmore Delay Steiner Tree Problem*, which is a key problem in VLSI design: We are given a set of pins which have to be connected by a Steiner tree. One of the pins is the source. Challenging timing constraints impose tight bounds on the delay of propagating a signal from the source to the other pins. The commonly used measure is Elmore delay (Elmore in J Appl Phys 19:55–63, 1948). We consider two variants: minimizing the maximum Elmore delay or a weighted sum of Elmore delays. Both variants are strongly *NP*-hard even for very restricted special cases. Although it is a central problem in VLSI design (Kahng and Robins in On optimal interconnections for VLSI. Kluwer, Boston, 1995; Korte and Vygen in Building bridges—between mathematics and computer science. Springer, Berlin, pp 333–368, 2008), no approximation algorithms were known so far. In this work, we give the first constant-factor approximation algorithm. It works for both variants. The algorithm achieves an approximation ratio of 3.39 in the rectilinear plane and 4.11 in general metric spaces. We can show that our algorithm is best possible in a certain sense. We also demonstrate that our algorithm leads to improvements on real world VLSI instances compared to the currently used standard method of computing short Steiner trees.

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## Notes

- 1.
The Hanan grid is the grid that is induced by the set of

*x*- and*y*-coordinates of all terminals—see Hanan [18]. - 2.
The

*Shortest Steiner Tree Problem*is the problem of finding a Steiner tree*Y*with*l*(*Y*) minimum. It is more commonly referred to as*Minimum Steiner Tree Problem*, but since in our application edge weights can most suitably be regarded as lengths, we will use this term instead. - 3.
Every general Steiner tree can be transformed into such a tree in linear time by adding additional Steiner points and edges of length 0.

- 4.
Here we assume \(\tau = \varOmega (|V(Y_0)|)\).

- 5.
\(\beta \le 2\) can always be assumed by not using anything worse than a minimum spanning tree for the terminal set as initial solution.

- 6.
A rectilinear minimum spanning tree can be computed in \(O(|T| \log |T|)\) time using only edges of the Delaunay Triangulation.

- 7.
The metric closure of a graph \(G=(V,E)\) with edge lengths \(l:E \rightarrow {\mathbb {R}}_{\ge 0}\) is defined as the complete graph with vertex set

*V*and a metric distance function*dist*such that*dist*(*v*,*w*) equals the length of a shortest path between*v*and*w*with respect to*l*in*G*. - 8.
The actual algorithm used depends on the size of the terminal set.

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## Acknowledgments

We would like to thank Jens Vygen for his helpful comments and support.

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Scheifele, R. Steiner Trees with Bounded RC-Delay.
*Algorithmica* **78, **86–109 (2017). https://doi.org/10.1007/s00453-016-0149-4

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### Keywords

- Steiner trees
- Approximation algorithm
- VLSI design